Soft N-modular redundancy

IEEE Transactions on Computers

Volumn 61, Issue 3, 2012, Pages 323-336

  Kim, Eric P ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Low power design; redundant design; signal processing systems

Indexed keywords

BAYESIAN DETECTION; CMOS PROCESSS; ENERGY EFFICIENT; ERROR DETECTION AND CORRECTION; IMAGE CODER; LOW-POWER DESIGN; MAJORITY VOTER; N-MODULAR REDUNDANCIES; NANO SCALE; NANOSCALE CMOS; POWER SAVINGS; REDUNDANT DESIGN; SIGNAL PROCESSING SYSTEMS; VOLTAGE VARIATION; VOLTAGE-SCALING;

CMOS INTEGRATED CIRCUITS; COST FUNCTIONS; DESIGN; DISCRETE COSINE TRANSFORMS; ERROR DETECTION; ERROR STATISTICS; FAULT DETECTION; FAULT TOLERANCE; IMAGE CODING; NANOTECHNOLOGY; REDUNDANCY; SIGNAL PROCESSING;

ENERGY EFFICIENCY;

EID: 84856267929     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2010.253     Document Type: Article

References (27)

1. Int'l Technology Roadmap for Semiconductors 2008 Update, Int'l Technology Roadmap for Semiconductors. http://www.itrs.net/Links/2008ITRS/Home2008.htm. 2008.
2. Y. Cao and L. Clark, "Mapping Statistical Process Variations toward Circuit Performance Variability: An Analytical Modeling Approach," IEEE Trans. Computer-Aided Design of Integrated Circuits and System, vol. 26, no. 10, pp. 1866-1873, Oct. 2007. (Pubitemid 47483026)
3. D. Ernst et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture, pp. 7-18, Dec. 2003.
4. R. Hegde and N.R. Shanbhag, "Soft Digital Signal Processing," IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 6, pp. 813-823, Dec. 2001. (Pubitemid 34126213)
5. G.V. Varatkar, S. Narayanan, N.R. Shanbhag, and D. Jones, "Sensor Network-on-Chip," Proc. Int'l Symp. System-on-Chip, pp. 1-4, Nov. 2007.
6. E. Karl, D. Sylvester, and D. Blaauw, "Timing Error Correction Techniques for Voltage-Scalable On-Chip Memories," Proc. Int'l Symp. Circuits and Systems (ISCAS), vol. 4, pp. 3563-3566, May 2005.
7. G.V. Varatkar and N.R. Shanbhag, "Error-Resilient Motion Estimation Architecture," IEEE Trans. Very Large Scale Integration Systems, vol. 16, no. 10, pp. 1399-1412, Oct. 2008.
8. R. Abdallah and N. Shanbhag, "Error-Resilient Low-Power Viterbi Decoder Architectures," IEEE Trans. Signal Process., vol. 57, no. 12, pp. 4906-4917, Dec. 2009.
9. J. Von Neumann, "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components," Automata Studies, pp. 43-98, Princeton Univ. Press, 1956.
10. W. Brown, J. Tierney, and R. Wasserman, "Improvement of Electronic-Computer Reliability through the Use of Redundancy," IEEE Trans. Electronic Computer, vol. EC-10, no. 3, pp. 407-416, Sept. 1961.
11. N. Vaidya and D. Pradhan, "Fault-Tolerant Design Strategies for High Reliability and Safety," IEEE Trans. Computer, vol. 42, no. 10, pp. 1195-1206, Oct. 1993.
12. I. Koren and S. Su, "Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults," IEEE Trans. Computer, vol. C-28, no. 7, pp. 514-520, July 1979. (Pubitemid 9477373)
13. Y. Tamir, M. Tremblay, and D. Rennels, "The Implementation and Application of Micro Rollback in Fault-Tolerant VLSI Systems," Proc. IEEE Fault-Tolerant Computing Symp., pp. 234-239, 1988.
14. S.J. Piestrak, "Design of Fast Self-Testing Checkers for a Class of Berger Codes," IEEE Trans. Computer, vol. C-36, no. 5, pp. 629-634, May 1987.
15. A. Avizienis, "Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design," IEEE Trans. Computer, vol. C-20, no. 11, pp. 1322-1331, Nov. 1971.
16. N.R. Shanbhag, "Reliable and Efficient System-on-a-Chip Design," IEEE Computer, vol. 37, no. 3, pp. 42-50, Mar. 2004.
17. E.P. Kim, R.A. Abdallah, and N.R. Shanbhag, "Soft NMR: Exploiting Statistics for Energy-Efficiency," Proc. Int'l Symp. System-on-Chip (SOC), pp. 52-55, Oct. 2009.
18. P. Huber, Robust Statistics. Wiley, 1981.
19. H. Poor, An Introduction to Signal Detection and Estimation. Springer-Verlag, 1994.
20. D. Blough and G. Sullivan, "A Comparison of Voting Strategies for Fault-Tolerant Distributed Systems," Proc. Ninth Symp. Reliable Distributed Systems, pp. 136-145, Oct. 1990.
21. W.-H. Chen, C. Smith, and S. Fralick, "A Fast Computational Algorithm for the Discrete Cosine Transform," IEEE Trans. Comm., vol. C-25, no. 9, pp. 1004-1009, Sept. 1977. (Pubitemid 8564969)
22. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, second ed. Pearson Education, 2003.
23. S. Mitra and E. McCluskey, "Word-Voter: A New Voter Design for Triple Modular Redundant Systems," Proc. 18th IEEE Very Large Scale Integration Systems Test Symp. (VLSI), pp. 465-470, 2000.
24. C.T. Kong, "Study of Voltage and Process Variations Impact on the Path Delays of Arithmetic Units," MS thesis, Univ. of Illinois, May 2008.
25. E.P. Kim and N.R. Shanbhag, "Soft NMR: Analysis and Application to DSP Systems," Proc. Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP), pp. 1494-1497, Mar. 2010.
26. Int'l Telecomm. Union, "JPEG Standard," ITU-T Recommendation T.81, 1993.
27. S. Thoziyoor, N. Muralimanohar, and N. Jouppi, "CACTI 5.0," Technical Report HPL-2007-167, Hewlett Packard Laboratories, 2007.