FPGA-based image processor architecture for Wireless Multimedia Sensor Network

Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011

Volumn , Issue , 2011, Pages 100-105

  Pham, Duc Minh ^a   Aziz, Syed Mahfuzul ^a  

^a UNIVERSITY OF SOUTH AUSTRALIA   (Australia)

Author keywords

Coprocessors; Digital integrated circuits; Image processing; Microprocessors; Wireless Sensor Networks

Indexed keywords

CO-PROCESSORS; HIGH FREQUENCY; HIGH-SPEED PROCESSING; IMAGE PROCESSING FUNCTIONS; IMAGE PROCESSORS; LOW FREQUENCY; PACKETIZATION; POWER MANAGEMENTS; PROCESSING SYSTEMS; RISC MICROPROCESSORS; SYSTEM SYNCHRONIZATION; WIRELESS MULTIMEDIA SENSOR NETWORK; WIRELESS SENSOR;

COMPUTER ARCHITECTURE; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENERGY MANAGEMENT; EXPERIMENTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HUMAN COMPUTER INTERACTION; IMAGE COMPRESSION; IMAGE PROCESSING; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; OPTIMIZATION; UBIQUITOUS COMPUTING;

WIRELESS SENSOR NETWORKS;

EID: 84855773327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUC.2011.38     Document Type: Conference Paper

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