|
Volumn , Issue , 2011, Pages 263-266
|
Application of the latency insertion method to electro-thermal circuit analysis
|
Author keywords
circuit simulation; electro thermal analysis; IR drop; latency insertion; power integrity
|
Indexed keywords
DESIGN STAGE;
ELECTRO-THERMAL ANALYSIS;
HIGH PERFORMANCE SYSTEMS;
INTERCONNECT NETWORKS;
IR DROP;
LATENCY INSERTION;
LATENCY INSERTION METHODS;
OFF-CHIP;
ON CHIPS;
POWER INTEGRITY;
SIMULATION TECHNIQUE;
THERMAL PHENOMENA;
CHIP SCALE PACKAGES;
CIRCUIT SIMULATION;
THERMOANALYSIS;
THREE DIMENSIONAL;
VLSI CIRCUITS;
ELECTRIC NETWORK ANALYSIS;
|
EID: 84855393103
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/EPEPS.2011.6100242 Document Type: Conference Paper |
Times cited : (3)
|
References (9)
|