Annealing of stress-induced interface and border traps in MOS devices: A charge-pumping study

European Solid-State Device Research Conference

Volumn , Issue , 1996, Pages 851-854

  Autran, J L ^a   Flament, O ^a   Chabrerie, C ^a,b   Musseau, O ^a   Leray, J L ^a  

^a CEA DIF   (France)

^b THALES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BORDER TRAPS; STRESS-INDUCED;

EID: 8444226652     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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