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2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
Volumn , Issue , 2011, Pages 122-127
A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering
Author keywords

high parallel; LDPC decoder; low power; matrix reordering
Indexed keywords

CLOCK CYCLES; CODE LENGTH; CODE RATES; HARDWARE COST; HIGH PARALLEL; LDPC CODES; LDPC DECODER; LOW DENSITY PARITY CHECK; LOW POWER; MACRO BLOCK; MATRIX; MEMORY BITS; QUASI-CYCLIC; WIMAX STANDARDS;
EID: 84055177254     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SiPS.2011.6088961     Document Type: Conference Paper
Times cited : (3)
References (8)
  • 2
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    • Ph.D. dissertation, Electrical Engineering, Univ. Linkoping, Linkoping, Sweden
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  • 3
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  • 4
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    • Sun, Y.1    Karkooti, M.2    Cavallaro, J.R.3
  • 5
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    • A 4.84 mm2 847-955 Mb/s 397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for the WiMAX System in 0.13 μm CMOS
    • Feb.
    • B. Xiang and X. Zeng, "A 4.84 mm2 847-955 Mb/s 397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for the WiMAX System in 0.13 μm CMOS,", Symp. on VLSI Circuits Dig. Tech. Papers, pp. 211-212, Feb. 2010
    • (2010) Symp. on VLSI Circuits Dig. Tech. Papers , pp. 211-212
    • Xiang, B.1    Zeng, X.2
  • 6
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    • X.-Y. Shih, et al., "An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 CMOS Process,"IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 684-694, Mar. 2008.
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  • 7
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    • High Parallel Variation Banyan Network Based Permutation Network for Reconfigurable LDPC Decoder
    • July
    • X. Peng, Z. Chen, X Zhao, F. Maehara, S. Goto, "High Parallel Variation Banyan Network Based Permutation Network for Reconfigurable LDPC Decoder," Proc. IEEE ASAP, pp. 233-238, July, 2010.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.