Leveraging torus topology with deadlock recovery for cost-efficient on-chip network

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2011, Pages 25-30

  Shin, Minjeong ^a   Kim, John ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BISECTION BANDWIDTH; COST-EFFICIENT; DATA PATHS; DEADLOCK AVOIDANCE; DEADLOCK RECOVERY; MESH NETWORK; MESH TOPOLOGIES; ON CHIPS; ON-CHIP NETWORKS; TIMEOUT MECHANISM; TORUS NETWORKS; VIRTUAL CHANNELS;

COMPUTER GRAPHICS; EMBEDDED SYSTEMS; MESH NETWORKING; RECOVERY; TOPOLOGY;

COMPUTER SYSTEM RECOVERY;

EID: 83455259865     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2011.6081371     Document Type: Conference Paper

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