High speed partial run-time reconfiguration using enhanced ICAP hard macro

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum

Volumn , Issue , 2011, Pages 174-180

  Hansen, Simen Gimle ^a   Koch, Dirk ^a   Torresen, Jim ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

Enhanced ICAP hard macro; Field programmable gate array (FPGA); High speed partial run time reconfiguration; Internal Configuration Access Port (ICAP)

Indexed keywords

FABRICATION PROCESS; FPGA VENDORS; HARD MACRO; HIGH SPEED PARTIAL RUN-TIME RECONFIGURATION; HIGH-SPEED; IMPLEMENTATION METHODS; INTERNAL CONFIGURATION ACCESS PORTS; NEW DESIGN; OVERCLOCKING; PARTIAL RECONFIGURATION; PARTIAL RUN-TIME RECONFIGURATION; RUN TIME RECONFIGURATION;

DISTRIBUTED PARAMETER NETWORKS; MACROS; SPEED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 83455188215     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2011.139     Document Type: Conference Paper

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