A low power, wide dynamic range multigain signal processor for the SNAP CCD

IEEE Transactions on Nuclear Science

Volumn 51, Issue 5 I, 2004, Pages 1936-1941

  Walder, J P ^a   Chao, G ^a   Genat, J F ^b   Karcher, A ^a   Krieger, B ^a   Kurz, S ^a   Steckert, J ^a   Von der Lippe, H ^a  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^b UNIVERSITÉ PARIS DIDEROT   (France)

Author keywords

Analog processing circuits; Charge coupled devices; CMOS analog integrated circuits; Correlated double sampling

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CHARGE COUPLED DEVICES; COMPUTER SIMULATION; ENERGY UTILIZATION; IMAGE ANALYSIS; MICROPROCESSOR CHIPS; OPTIMIZATION; SATELLITES; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

ANALOG PROCESSING CIRCUITS; CMOS ANALOG INTEGRATED CIRCUITS; CORRELATED DOUBLE SAMPLING; SUPER NOVA/- ACCELERATION PROBE (SNAP);

CMOS INTEGRATED CIRCUITS;

EID: 8344261735     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.834717     Document Type: Article

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