A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip

European Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 159-162

  Ickes, Nathan ^a   Sinangil, Yildiz ^a   Pappalardo, Francesco ^b   Guidetti, Elio ^b   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY VOLTAGE; DATA CACHES; ENERGY BUDGETS; FLASH ROM; LOW-VOLTAGE; MEMORY ACCESS; ON-CHIP CLOCK GENERATION; PEAK PERFORMANCE; PROCESSING LOAD; SYSTEM ON CHIPS; SYSTEM-ON-CHIP; TIME VARYING; ULTRA-LOW-VOLTAGE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE; TIME VARYING NETWORKS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 82955225008     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6044889     Document Type: Conference Paper

References (16)

1. B. A. Warneke and K. S. Pister, "An ultra-low energy microcontroller for Smart Dust wireless sensor networks," in Proc. ISSCC, February 2004.
2. V. Ekanayake, I. Clinton Kelly, and R. Manohar, "An ultra low-power processor for sensor networks," in Proc. ASPLOS, 2004, pp. 27-36.
3. L. Nazhandali, M. Minuth, B. Zhai, J. Olson, T. Austin, and D. Blaauw, "A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution," in Proc. CASES, 2005, pp. 249-256.
4. N. Ickes, D. Finchelstein, and A. P. Chandrakasan, "A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications," in IEEE Asian Solid State Circuits Conference, 2008, pp. 289-292.
5. J. Kwong and A. P. Chandrakasan, "An energy-efficient biomedical signal processing platform," in IEEE European Solid-State Circuits Conf. (ESSCIRC) Dig. Tech. Papers, 2010, pp. 526-529.
6. M. Ashouei, J. Hulzink, M. Konijnenburg, J. Zhou, F. Duarte, A. Breeschoten, J. Huisken, J. Stuyt, H. de Groot, F. Barat, J. David, and J. V. Ginderdeuren, "A voltage-scalable biomedical signal processor running ECG using 13 pJ/cycle at 1MHz and 0.4 V," in Proc. ISSCC, 2011, pp. 332-334.
7. S. R. Sridhara, M. DiRenzo, S. Lingam, S.-J. Lee, R. Blázquez, J. Maxey, S. Ghanem, Y.-H. Lee, R. Abdallah, P. Singh, and M. Goel, "Microwatt embedded processor platform for medical system-on-chip applications," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 721-730, 2011.
8. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond," in Proc. VLSI, Jun. 2005, pp. 128-129.
9. B. H. Calhoun and A. Chandrakasan, "A 256 kb sub-threshold SRAM in 65 nm CMOS," in Proc. ISSCC, Feb. 2006, pp. 2592-2593.
10. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A read-static-noise-margin-free SRAM cell for low- VDD and high-speed applications," in Proc. ISSCC, Feb. 2005, pp. 478-479.
11. N. Verma and A. P. Chandrakasan, "A 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy," in Proc. ISSCC, Feb. 2007, pp. 328-606.
12. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply," in Proc. ISSCC, Feb. 2005, pp. 474-475.
13. T.-H. Kim, J. Liu, J. Keane, and C. H. Kim, "A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme," in Proc. ISSCC, Feb. 2007, pp. 330-331.
14. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "Low-power embedded SRAM modules with expanded margins for writing," in Proc. ISSCC, Feb. 2005, pp. 480-481.
15. M. E. Sinangil, H. Mair, and A. P. Chandrakasan, "A 28 nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V," in Proc. ISSCC, Feb. 2011, pp. 260-262.
16. D. J. Wheeler and R. M. Needham, "TEA, a tiny encryption algorithm,"Lecture Notes in Computer Science, vol. 1008, pp. 363-366, 1995.