Design of an ultra high speed AES processor for next generation IT security

Computers and Electrical Engineering

Volumn 37, Issue 6, 2011, Pages 1160-1170

  Ali, Liakot ^a   Aris, Ishak ^b   Hossain, Fakir Sharif ^a   Roy, Niranjan ^a  

^a BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY   (Bangladesh)

^b UNIVERSITY PUTRA MALAYSIA   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED ENCRYPTION STANDARD; AES ALGORITHMS; ALGEBRAIC OPERATIONS; DATA PATHS; IT SECURITY; IT SYSTEM; LOW LATENCY; NEW DIMENSIONS; SOFT-CORES; ULTRA HIGH SPEED; VERILOG HDL;

DATA PRIVACY; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SECURITY SYSTEMS; SPEED;

CRYPTOGRAPHY;

EID: 82655181942     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2011.06.003     Document Type: Article

References (35)

1. W. Stallings Cryptography and Network Security: Principles and Practices 3rd ed. 2003 Pearson Education (Singapore) Pte. Ltd. Indian Branch pp. 30-140
2. A. Eskicioglu, and L. Litwin Cryptography, IEEE 21 1 2001 36 38
3. Federal Information Processing Standards Publication (FIPS PUB) 197, National Institute of Standards and Technology (NIST). Advanced encryption standard (AES). Available: ; 2001.
4. Leopld G. U.S. unveils advanced encryption standard. EE Times. Available: ; 2001.
5. Gielata A, Russek P, Wiatr K. AES hardware implementation in FPGA for algorithm acceleration purpose. In: Proceedings of International Conference on Signals and Electronic Systems; 2008. p. 137-40.
6. M. McLoone, and J. McCanny Rijndael FPGA implementations utilizing look-up tables Journal of VLSI Signal Processing 34 2003 261 275
7. Järvinen KU, Tommiska MT, Skyttä JO. A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In: Proceedings of the International Symposium on Field Programmable Gate Arrays; 2003. p. 207-15.
8. Joarvinen K. Study on high-speed hardware implementation of cryptographic algorithms, Department of Signal Processing and Acoustics, Helsinki University of Technology; 2009.
9. Standaert F, Rouvroy G, Quisquater J, Legat J. Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs. In: Proceedings of the CHES 2003, LNCS 2779; 2003. p. 334-50.
10. Saggese GP, Mazzeo A, Mazzocca N, Strollo AGM. An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Proceedings of the FPL 2003, LNCS 2778; 2003. p. 292-302.
11. Hodjat A, Verbauwhede I. A 21.54 Gbits/s fully pipelined AES processor on FPGA. In: Proceedings of the 12th IEEE symposium on field-programmable custom computing machines; 2005. p. 308-9.
12. X. Zhang, and K. Parhi High-speed VLSI architectures for the AES algorithm IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 2004 957 967
13. Granado-Criado JM, Vega-Rodriguez Miguel A, Sanchez Perz Juan M, Gomez- Pulido Juan A. A new methodology to implement the AES algorithm using partial and dynamic reconfiguration, Department Technologies of Computers and Communications, University of Extremadura, Spain; 2009.
14. S.-M. Yoo, D. Kotturi, D.W. Pan, and J. Blizzard An AES crypto chip using a high-speed parallel pipelined architecture Microprocessors and Microsystems 29 2005 317 326 (Pubitemid 41023806)
15. Saleh AH, Ahmed SSB. High performance AES design using pipelining structure over GF ((24)2). In: Proceedings of IEEE International Conference on Signal Processing and Communications; 2007. p. 716-9.
16. Rady A, ElSehely E, ElHennawy AM. Design and implementation of area optimized AES algorithm on reconfigurable FPGA. In: Proceedongs of international conference on microelectronics; 2007. p. 35-8.
17. Rais MH, Qasim SM. A novel FPGA implementation of AES-128 using reduced residue of prime numbers based S-Box. In: IJCSNS international journal of computer science and network security, vol. 9(9); 2009. p. 305.
18. Rohiem AE, Ahmen FM, Mustafa AM. FPGA implementation of reconfigurable parameters AES algorithm. In: 13th international conference on aerospace sciences & aviation technology, ASAT; 2009. p. 26-8.
19. Henriquez FR, Saqib NA, Perez AD. 4.2 Gbit/s single-chip FPGA implementation of AES algorithm. Electron Lett 2003;39(15):1115-6.
20. Gaj K, Chodowiec P. Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays. In: Proceedings of the CT-RSA 2001, LNCS 2020; 2001. p. 84-99. (Pubitemid 33255157)
21. Dyken JV, Delgado-Frias JG. FPGA schemes for minimizing the power-throughput trade-off in executing the advanced encryption standard algorithm. Journal of Systems Architecture: The EUROMICRO Journal 2010;56(2-3).
22. Wolkerstorfer J, Oswald E, Lamberger M. An ASIC implementation of the AES Sbox. In: Proceedings of the RSA conference 2002, San Jose, CA; 2002.
23. Verbauwhede I, Schaumont P, Kuo H. Design and performance testing of a 2.29 Gb/s rijndael processor. IEEE Journal of Solid-State Circuits 2003:569-72.
24. Satoh A. A compact Rijndeal hardware architecture with S-box optimization. ASIACRYPT 2001, LNCS 2248; 2001. p. 239-54. (Pubitemid 33371189)
25. Morioka S, Satoh A. A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture. In: IEEE transaction on very large scale integration systems, vol. 12(7); 2004. p. 686-91.
26. Hodjat A, Verbauwhede I. Minimum area cost for a 30 to 70 Gb/s AES processor. In: IEEE computer society annual symposium on VLSI, emerging trends in VLSI systems design; 2004. p. 83-8.
27. Hodjat A, Verbauwhede I. Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor. In: 37th Asilomar conference on signals, systems, and computers; 2003. p. 2147-50.
28. Hodjat A, Verbauwhede I. Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. In: IEEE transactions on computers, vol. 55(4); 2006. p. 366-72.
29. Su C, Lin T, Huang C, Wu C. A high-throughput low-cost AES processor. In: IEEE communication magazine; 2003. p. 86-91.
30. Schramm K, Paar C. Higher-order masking of the AES", CT-RSA, lecture notes in computer science (LNCS), vol. 3860; 2006. p. 208-25.
31. Roy N, Ali L. Design of an ultra high speed crypto processor ASIC. In: Cool chips: IEEE symposium on low power and high-speed chips; 2008. p. 118.
32. Oswald E, Mangard S, Herbst C, Tillich S. Practical second-order differential power analysis (DPA) attacks for masked smart card implementations of block ciphers. In: CT-RSA, lecture notes in computer science (LNCS), vol. 3860; 2006. p. 192-207. (Pubitemid 43971710)
33. Bertoni G, Macchetti M, Negri L. Power-efficient ASIC synthesis of cryptographic S-boxes. In: Proceedings of the great lake symposium on VLSI (GLSVLSI), Association for Computing Machinery (ACM) Press; 2004. p. 277-81.
34. Wang S, Ni W. An efficient FPGA implementation of advanced encryption standard algorithm. In: Proceedings of international symposium on circuits and systems (ISCAS), vol. 2; 2004. p. 597-600.
35. Alaoui C. New experimental results for AES-CCMP acceleration on cyclone-II FPGA. In: IJCSNS international journal of computer science and network security, vol. 10(4); 2010.