LEARNING AND OPTIMIZATION WITH CASCADED VLSI NEURAL NETWORK BUILDING-BLOCK CHIPS

Proceedings of the International Joint Conference on Neural Networks

Volumn 1, Issue , 1992, Pages 184-189

  Duong, T ^a   Eberhardt, S P ^a   Tran, M ^a   Daud, T ^a   Thakoor, A P ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL OPTIMIZATION; COMPUTER HARDWARE; DIGITAL TO ANALOG CONVERSION; GRADIENT METHODS; LEARNING SYSTEMS; NEURAL NETWORKS; VLSI CIRCUITS;

ANALOG VLSI; BLOCK APPROACH; BLOCK CHIPS; BUILDING BLOCKES; DIGITAL-TO-ANALOG CONVERTERS; NETWORK BUILDING BLOCKS; NEURAL-NETWORKS; OPTIMISATIONS; PARITY PROBLEMS; VLSI CHIP;

LEARNING ALGORITHMS;

EID: 82455176092     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.1992.287138     Document Type: Conference Paper

References (12)

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