Hardware in the Loop test for power system modeling and simulation

2006 IEEE PES Power Systems Conference and Exposition, PSCE 2006 - Proceedings

Volumn , Issue , 2006, Pages 1892-1897

  Wu, Jian ^a   Cheng, Yong ^a   Srivastava, Anurag K ^b,c   Schulz, Noel N ^a   Ginn III, Herbert L ^a  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^c ASIAN INSTITUTE OF TECHNOLOGY   (Thailand)

Author keywords

Hardware In the loop; Microprocessor; Relay DSP

Indexed keywords

ACTIVE COMPENSATOR; DESIGN PROCEDURE; DEVICE DESIGN; GENERAL FUNCTIONS; HARD-WARE-IN-THE-LOOP; HARDWARE IN THE LOOPS; HARDWARE-IN-THE-LOOP TESTS; HIL SIMULATIONS; MICROPROCESSOR; NEW DEVICES; PHYSICAL COMPONENTS; POWER DEVICES; POWER SYSTEM MODELING; RELAY DSP; RELAY TEST; SYSTEM CONDITIONS;

COMPUTER SIMULATION; DESIGN; REAL TIME SYSTEMS; TESTING;

POWER TRANSMISSION;

EID: 81755176158     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PSCE.2006.296201     Document Type: Conference Paper

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