-
1
-
-
33748989811
-
CMOL: Devices, circuits, and architectures
-
DOI 10.1007/3-540-31514-4-17, Introducing Molecular Electronics
-
K.K. Likharev and D. B. Strukov, "CMOL: Devices, circuits, and architectures," in Introducing Molecular Electronics (Lecture Notes in Physics), vol. 680, G. Cuniberti, K. Richter, and G. Fagas, Eds. Berlin, Germany: Springer-Verlag, 2005, pp. 447-477. (Pubitemid 44445609)
-
(2006)
Lecture Notes in Physics
, vol.680
, pp. 447-477
-
-
Likharev, K.K.1
Strukov, D.B.2
-
2
-
-
77950852717
-
Memristive switches enable stateful logic operations via material implication
-
J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, "Memristive switches enable stateful logic operations via material implication," Nature, vol. 464, no. 7290, pp. 873-876, 2010.
-
(2010)
Nature
, vol.464
, Issue.7290
, pp. 873-876
-
-
Borghetti, J.1
Snider, G.S.2
Kuekes, P.J.3
Yang, J.J.4
Stewart, D.R.5
Williams, R.S.6
-
3
-
-
43049126833
-
The missing memristor found
-
DOI 10.1038/nature06932, PII NATURE06932
-
D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, 2008. (Pubitemid 351630336)
-
(2008)
Nature
, vol.453
, Issue.7191
, pp. 80-83
-
-
Strukov, D.B.1
Snider, G.S.2
Stewart, D.R.3
Williams, R.S.4
-
4
-
-
33745327664
-
Ge/Si nanowire heterostructures as high-performance field-effect transistors
-
DOI 10.1038/nature04796, PII NATURE04796
-
J. Xiang,W. Lu, Y. Hu, Y.Wu, H. Yan, and C. M. Lieber, "Ge/Si nanowire heterostructures as high-performance field-effect transistors," Nature, vol. 441, no. 25, pp. 489-493, 2006. (Pubitemid 44050147)
-
(2006)
Nature
, vol.441
, Issue.7092
, pp. 489-493
-
-
Xiang, J.1
Lu, W.2
Hu, Y.3
Wu, Y.4
Yan, H.5
Lieber, C.M.6
-
5
-
-
0037392525
-
Nanoscale molecularswitch crossbar circuits
-
Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li,D. R. Stewart, J.O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams, "Nanoscale molecularswitch crossbar circuits," Nanotechnology, vol. 14, pp. 462-468, 2003.
-
(2003)
Nanotechnology
, vol.14
, pp. 462-468
-
-
Chen, Y.1
Jung, G.-Y.2
Ohlberg, D.A.A.3
Li, X.4
Stewart, D.R.5
Jeppesen, J.O.6
Nielsen, K.A.7
Stoddart, J.F.8
Williams, R.S.9
-
6
-
-
13644283486
-
The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits
-
P. J. Kuekes, D. R. Stewart, and R. S. Williams, "The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits," J. Appl. Phys., vol. 97, pp. 034 301-1-034 301-5, 2005.
-
(2005)
J. Appl. Phys.
, vol.97
, pp. 0343011-0343015
-
-
Kuekes, P.J.1
Stewart, D.R.2
Williams, R.S.3
-
7
-
-
4344644019
-
CMOS-like logic in defective, nanoscale crossbars
-
G. S. Snider, P. J. Kuekes, and R. S. Williams, "CMOS-like logic in defective, nanoscale crossbars," Nanotechnology, vol. 15, pp. 881-891, 2004.
-
(2004)
Nanotechnology
, vol.15
, pp. 881-891
-
-
Snider, G.S.1
Kuekes, P.J.2
Williams, R.S.3
-
8
-
-
35748932911
-
Nanoelectronics from the bottom up
-
DOI 10.1038/nmat2028, PII NMAT2028
-
W. Lu and M. L. Charles, "Nanoelectronics from the bottom up," Nat. Mater., vol. 6, pp. 841-850, 2007. (Pubitemid 350050579)
-
(2007)
Nature Materials
, vol.6
, Issue.11
, pp. 841-850
-
-
Lu, W.1
Lieber, C.M.2
-
9
-
-
12344261603
-
Prospects for terabit-scale nanoelectronic memories
-
DOI 10.1088/0957-4484/16/1/028
-
D. B. Strukov and K. K. Likharev, "Prospects for terabit-scale nanoelectronic memories," Nanotechnology, vol. 16, pp. 137-148, 2005. (Pubitemid 40121546)
-
(2005)
Nanotechnology
, vol.16
, Issue.1
, pp. 137-148
-
-
Strukov, D.B.1
Likharev, K.K.2
-
10
-
-
18744373862
-
CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
-
DOI 10.1088/0957-4484/16/6/045, PII S0957448405943274
-
D. Strukov and K. Likharev,"CMOLFPGA:Areconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 6, pp. 888-900, 2005. (Pubitemid 40666599)
-
(2005)
Nanotechnology
, vol.16
, Issue.6
, pp. 888-900
-
-
Strukov, D.B.1
Likharev, K.K.2
-
11
-
-
15844407659
-
Architectures for nanoelectronic implementation of artificial neural networks: New results
-
DOI 10.1016/j.neucom.2004.11.023, PII S0925231204005132
-
O. Türel, J. H. Lee, X. Ma, and K. K. Likharev, "Architectures for nanoelectronic implementation of artificial neural networks: New results," Neurocomputing, vol. 64, pp. 271-283, 2005. (Pubitemid 40425323)
-
(2005)
Neurocomputing
, vol.64
, Issue.1-4 SPEC. ISS.
, pp. 271-283
-
-
Turel, O.1
Lee, J.H.2
Ma, X.3
Likharev, K.K.4
-
12
-
-
67249153542
-
A theoretical investigation on CMOL FPGA cell assignment problem
-
May
-
G. Chen, X. Song, and P. Hu, "A theoretical investigation on CMOL FPGA cell assignment problem," IEEE Trans. Nanotechnol., vol. 8, no. 3, pp. 322-329, May 2009.
-
(2009)
IEEE Trans. Nanotechnol.
, vol.8
, Issue.3
, pp. 322-329
-
-
Chen, G.1
Song, X.2
Hu, P.3
-
14
-
-
33846807711
-
Nano/CMOS architectures using a fieldprogrammable nanowire interconnect
-
G. Snider and R. Williams, "Nano/CMOS architectures using a fieldprogrammable nanowire interconnect," Nanotechnology, vol. 18, pp. 1-11, 2007.
-
(2007)
Nanotechnology
, vol.18
, pp. 1-11
-
-
Snider, G.1
Williams, R.2
-
15
-
-
34447115730
-
Three-dimensional CMOL: Three-dimensional integration of CMOS/nanomaterial hybrid digital circuits
-
DOI 10.1049/mnl:20070034
-
D. Tu, M. Liu, W. Wang, and S. Haruehanroengra, "Three-dimensional CMOL: Three-dimensional integration of CMOS/nanomaterial hybrid digital circuits," IET Micro Nano Lett., vol. 2, no. 2, pp. 40-45, 2007. (Pubitemid 47035542)
-
(2007)
Micro and Nano Letters
, vol.2
, Issue.2
, pp. 40-45
-
-
Tu, D.1
Liu, M.2
Wang, W.3
Haruehanroengra, S.4
-
16
-
-
73949132516
-
Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
-
D. B. Strukov and R. S. Williams, "Four-dimensional address topology for circuits with stacked multilayer crossbar arrays," Proc. Natl. Acad. Sci. USA, vol. 106, no. 48, pp. 20 155-20 158, 2010.
-
(2010)
Proc. Natl. Acad. Sci. USA
, vol.106
, Issue.48
, pp. 20155-20158
-
-
Strukov, D.B.1
Williams, R.S.2
-
17
-
-
77953108745
-
Monolithically stackable hybrid FPGA
-
Dresden,Germany,Aug.
-
D. Strukov and A. Mishchenko, "Monolithically stackable hybrid FPGA," in Proc.Design, Autom. Test Eur.,Dresden,Germany,Aug. 2010, pp. 661-666.
-
(2010)
Proc.Design, Autom. Test Eur.
, pp. 661-666
-
-
Strukov, D.1
Mishchenko, A.2
-
19
-
-
44649103871
-
Defect tolerant CMOL cell assignment via satisfiability
-
Jun.
-
W. N. N. Hung, C. Gao, X. Song, and D. Hammerstrom, "Defect tolerant CMOL cell assignment via satisfiability," IEEE Sensors J., vol. 8, no. 6, pp. 823-830, Jun. 2008.
-
(2008)
IEEE Sensors J.
, vol.8
, Issue.6
, pp. 823-830
-
-
Hung, W.N.N.1
Gao, C.2
Song, X.3
Hammerstrom, D.4
-
20
-
-
67650145870
-
A probabilistic memetic framework
-
Jun.
-
Q. H. Nguyen, Y.-S. Ong, and M. H. Lim, "A probabilistic memetic framework," IEEE Trans. Evol. Comput., vol. 13, no. 3, pp. 604-623, Jun. 2009.
-
(2009)
IEEE Trans. Evol. Comput.
, vol.13
, Issue.3
, pp. 604-623
-
-
Nguyen, Q.H.1
Ong, Y.-S.2
Lim, M.H.3
-
21
-
-
70349871709
-
Memetic algorithm with extended neighborhood search for capacitated arc routing problems
-
Oct.
-
K. Tang, Y. Mei, and X. Yao, "Memetic algorithm with extended neighborhood search for capacitated arc routing problems," IEEE Trans. Evol. Comput., vol. 13, no. 5, pp. 1151-1166, Oct. 2009.
-
(2009)
IEEE Trans. Evol. Comput.
, vol.13
, Issue.5
, pp. 1151-1166
-
-
Tang, K.1
Mei, Y.2
Yao, X.3
-
22
-
-
33847660505
-
A memetic algorithm for VLSI floorplanning
-
DOI 10.1109/TSMCB.2006.883268, Special Issue on Memetic Algorithms
-
M. Tang and X. Yao, "A memetic algorithm for VLSI floorplanning," IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 37, no. 1, pp. 62-69, Feb. 2007. (Pubitemid 46358480)
-
(2007)
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
, vol.37
, Issue.1
, pp. 62-69
-
-
Tang, M.1
Yao, X.2
-
23
-
-
78649828346
-
A memetic approach for nanoscale hybrid circuit cell mapping
-
Lille, France, Sep.
-
Z. Chu, Y. Xia, W. N. N. Hung, L. Wang, and X. Song, "A memetic approach for nanoscale hybrid circuit cell mapping," in Proc. 13th Euromicro Conf. Digital Syst. Design, Lille, France, Sep. 2010, pp. 681-688.
-
(2010)
Proc. 13th Euromicro Conf. Digital Syst. Design
, pp. 681-688
-
-
Chu, Z.1
Xia, Y.2
Hung, W.N.N.3
Wang, L.4
Song, X.5
-
24
-
-
44649101666
-
Cortical models onto CMOLandCMOS-Architectures and performance/price
-
Nov.
-
C. Gao and D. Hammerstrom, "Cortical models onto CMOLandCMOS-Architectures and performance/price," IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 54, no. 11, pp. 2502-2515, Nov. 2007.
-
(2007)
IEEE Trans. Circuits Syst. I: Fundam. Theory Appl.
, vol.54
, Issue.11
, pp. 2502-2515
-
-
Gao, C.1
Hammerstrom, D.2
-
25
-
-
0019477279
-
The Lagrangian relaxation method for solving integer programming problems
-
M. L. Fisher, "The Lagrangian relaxation method for solving integer programming problems," Manage. Sci., vol. 27, no. 1, pp. 1-18, 1981.
-
(1981)
Manage. Sci.
, vol.27
, Issue.1
, pp. 1-18
-
-
Fisher, M.L.1
-
26
-
-
0033892592
-
Lagrangian relaxation neural networks for job shop scheduling
-
DOI 10.1109/70.833193
-
P. B. Luh, X. Zhao, Y. Wang, and L. S. Thakur, "Lagrangian relaxation neural networks for job shop scheduling," IEEE Trans. Robot. Autom., vol. 16, no. 1, pp. 78-88, Feb. 2000. (Pubitemid 30593785)
-
(2000)
IEEE Transactions on Robotics and Automation
, vol.16
, Issue.1
, pp. 78-88
-
-
Luh, P.B.1
Zhao, X.2
Wang, Y.3
Thakur, L.S.4
-
27
-
-
0037389313
-
Timing-driven routing for FPGAs based on Lagrangian relaxation
-
Apr.
-
S. Lee and M. D. F. Wong, "Timing-driven routing for FPGAs based on Lagrangian relaxation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 4, pp. 506-510, Apr. 2003.
-
(2003)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.22
, Issue.4
, pp. 506-510
-
-
Lee, S.1
Wong, M.D.F.2
-
28
-
-
0003934798
-
SIS: A system for sequential circuit synthesis
-
Online]. Available
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, "SIS: A system for sequential circuit synthesis," EECS Dept., Univ. California, Berkeley, Tech. Rep.UCB/ERLM92/41, 1992. [Online]. Available: http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html
-
(1992)
EECS Dept., Univ. California, Berkeley, Tech. Rep.UCB/ERLM92/41
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni-Vincentelli, A.10
-
31
-
-
81255122948
-
Placement using simulated annealing
-
C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, Eds. Boca Raton, FL: CRC Press
-
W. Swartz, "Placement using simulated annealing," in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, Eds. Boca Raton, FL: CRC Press, 2008, pp. 311-325.
-
(2008)
Handbook of Algorithms for Physical Design Automation
, pp. 311-325
-
-
Swartz, W.1
-
32
-
-
36349012954
-
CMOL FPGA circuits
-
Las Vegas, NV
-
D. B. Strukov and K. K. Likharev, "CMOL FPGA circuits," in Proc. Int. Conf. Comput. Design, Las Vegas, NV, 2006, pp. 213-219.
-
(2006)
Proc. Int. Conf. Comput. Design
, pp. 213-219
-
-
Strukov, D.B.1
Likharev, K.K.2
-
33
-
-
0024913805
-
Combinational profiles of sequential benchmark circuits
-
F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. 1989 IEEE Int. Symp. Circuits Syst., Portland, OR, May 1989, pp. 1929-1934. (Pubitemid 20665296)
-
(1989)
Proceedings - IEEE International Symposium on Circuits and Systems
, vol.3
, pp. 1929-1934
-
-
Brglez Franc1
Bryan David2
Kozminski Krzysztof3
|