A lab-scale alternative interconnection solution of semiconductor dice compatible with power modules 3-d integration

IEEE Transactions on Power Electronics

Volumn 25, Issue 7, 2010, Pages 1667-1670

  Ménager, Ludovic ^a   Soueidan, Maher ^b   Allard, Bruno ^b   Bley, Vincent ^c,d   Schlegel, Benoît ^c,d  

^a UNIVERSITÉ GUSTAVE EIFFEL   (France)

^b UNIVERSITÉ DE LYON   (France)

^c UNIVERSITÉ DE TOULOUSE   (France)

^d Laboratoire Plasma et Conversion d'Energie   (France)

Author keywords

3 D packaging; Electroplating; power density; semiconductor die; transient liquid phase bonding

Indexed keywords

CHIP SCALE PACKAGES; COPPER; DIES; ELECTRIC POWER SYSTEMS; ELECTROPLATING; INTEGRATED CIRCUIT INTERCONNECTS; LIQUIDS; SUBSTRATES; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3D PACKAGING; ELECTRICAL CHARACTERIZATION; INTERCONNECTION TECHNOLOGY; POWER DENSITIES; POWER SEMICONDUCTORS; TRANSIENT LIQUID PHASE; TRANSIENT LIQUID PHASE BONDING; WIRE BONDING TECHNOLOGY;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 81155154419     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2010.2041557     Document Type: Article

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