A flexible parallel hardware architecture for AdaBoost-based real-time object detection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 6, 2011, Pages 1034-1047

  Kyrkou, Christos ^a   Theocharides, Theocharis ^a  

^a UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

Object detection; systolic arrays; VLSI

Indexed keywords

DETECTION ALGORITHM; FAVORABLE CONDITIONS; FRAME RATE; HARDWARE ARCHITECTURE; IMAGE FRAMES; INPUT IMAGE; LARGE IMAGES; OBJECT DETECTION; OBJECT DETECTION ALGORITHMS; OPERATING ENVIRONMENT; PARALLEL HARDWARE; REAL-TIME DETECTION; REGISTER TRANSFER LEVEL; SOFTWARE IMPLEMENTATION; VLSI;

ADAPTIVE BOOSTING; BIOINFORMATICS; COMPUTER APPLICATIONS; COMPUTER ARCHITECTURE; OBJECT RECOGNITION; PARALLEL ARCHITECTURES; SIGNAL DETECTION; SYSTOLIC ARRAYS;

COMPUTER HARDWARE;

EID: 80455172754     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2048224     Document Type: Article

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