Clock distribution networks in 3-D integrated systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 12, 2011, Pages 2256-2266

  Pavlidis, Vasilis F ^a   Savidis, Ioannis ^b   Friedman, Eby G ^b  

^a EPFL   (Switzerland)

^b University of Rochester   (United States)

Author keywords

3 D clock characterization; 3 D clock distribution; 3 D clock modeling; 3 D synchronization

Indexed keywords

3-D CLOCK CHARACTERIZATION; 3-D CLOCK DISTRIBUTION; 3-D CLOCK MODELING; 3-D INTEGRATION; 3-D SYNCHRONIZATION; CLOCK DISTRIBUTION; CLOCK SKEWS; DESIGN ISSUES; DESIGN OBJECTIVES; FUNDAMENTAL LIMITATIONS; INTEGRATED SYSTEMS; ON-CHIP INTERCONNECTS; PERFORMANCE CRITERION; TEST CIRCUIT;

CLOCK DISTRIBUTION NETWORKS; CLOCKS; DESIGN; ELECTRIC NETWORK TOPOLOGY; SYSTEMS ANALYSIS; TIMING JITTER; TOPOLOGY;

THREE DIMENSIONAL;

EID: 80455158008     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2073724     Document Type: Article

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