Scalable optical packet switch architecture for low latency and high load computer communication networks

International Conference on Transparent Optical Networks

Volumn , Issue , 2011, Pages

  Calabretta, Nicola ^a   Di Lucente, Stefano ^a   Nazarathy, Yoni ^a   Raz, Oded ^a   Dorren, Harmen ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

in band labels; label processor; optical interconnects; Optical packet switching; optical signal processing; optical switch

Indexed keywords

CLOCK CYCLES; COMPUTER COMMUNICATION NETWORKS; CONTENTION RESOLUTION; DATA CENTERS; DISTRIBUTED CONTROL; END-TO-END LATENCY; HIGH LOAD; HIGH PERFORMANCE COMPUTERS; IN-BAND LABELS; INPUT/OUTPUT; KEYPOINTS; LABEL PROCESSOR; LOW-LATENCY; MAXIMUM LOAD; NON-BLOCKING; OPTICAL DOMAINS; OPTICAL PACKET SWITCH ARCHITECTURE; OPTICAL PACKET SWITCHING; OPTICAL SIGNALS; PROCESSING SPEED; RECONFIGURATION TIME; STORAGE CAPACITY; SWITCH ARCHITECTURES; SWITCH MATRIX; SWITCHING TIME;

COMPUTER ARCHITECTURE; DISTRIBUTED PARAMETER CONTROL SYSTEMS; FIBER OPTIC NETWORKS; NETWORK ARCHITECTURE; OPTICAL COMMUNICATION; OPTICAL DATA STORAGE; OPTICAL INTERCONNECTS; OPTICAL SIGNAL PROCESSING; OPTICAL SWITCHES; PACKET SWITCHING; WIRELESS SENSOR NETWORKS;

TRANSPARENT OPTICAL NETWORKS;

EID: 80155167210     PISSN: None     EISSN: 21627339     Source Type: Conference Proceeding    
DOI: 10.1109/ICTON.2011.5971139     Document Type: Conference Paper

References (11)

1. L. Y. Lin et al.: Free-space micromachined optical switches with submillisecond switching time for largescale optical crossconnects, IEEE Photonics Technology Letters, 10(4), pp. 525-527, 1998.
2. R. Luijten et al.: Optical interconnection network: The OSMOSIS project, Lasers and Electro-Optics Society, vol. 2, pp. 563-564, 2004.
3. H. Wang et al.: Demonstration of a lossless monolithic 16x16 QW SOA switch, in Proc. ECOC 2009, post-deadline papers page 28 (PD 1.7), Vienna, Austria, 2009.
4. S. C. Nicholes et al.: The world's first InP 8×8 monolithic tunable optical router (MOTOR) operating at 40 Gbps line rate per port, in Proc. OFC 2009 post deadline paper B1, San Diego, USA, 2009.
5. V. E. Benes: Mathematical Theory of Connecting Networks and Telephone Traffic, (Academic, New York, 1965).
6. D. C. Opferman and N. T. Tsao-Wu: On a class of rearrangeable switching networks, Bell System Technical Journal, 50, 1579-1618 (1971)
7. N. Calabretta et al.: Optical packet switch sub-system with label processing and monolithically integrated InP optical switch, Photonics Society Winter Topicals Meeting Series (WTM), 2010 IEEE, pp. 107-108, 2010.
8. I. M. Soganci et al.: Integrated phased-array 1×16 photonic switch for WDM optical packet switching application, Photonics in Switching, 2009, PS '09, International Conference on, pp.1-2, 2009.
9. I. M. Soganci et al.: Monolithic InP 100-port photonic switch, in Proc. ECOC 2010,1-3 (2010).
10. N. Kikuchi et al.: Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG, IEEE Photonic Technology Letters, 16(11), pp. 2481-2483, 2004.
11. http://www.omnetpp.org/