Polysilicon gate depletion effect on deep-submicron circuit performance

1994 International Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, NUPAD 1994

Volumn , Issue , 1994, Pages 185-188

  Lin, W W ^a   Liang, Chunlin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUITS; NUMERICAL MODELS; POLYCRYSTALLINE MATERIALS; POLYSILICON; TIMING CIRCUITS;

CIRCUIT PERFORMANCE; COMPETING EFFECTS; DEEP SUB-MICRON; DEEP-SUBMICRON CIRCUITS; DOMINANCE BEHAVIOR; GATE OXIDE THICKNESS; LOW-POWER OPERATION; POLYSILICON GATES;

LOW POWER ELECTRONICS;

EID: 80155166322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NUPAD.1994.343461     Document Type: Conference Paper

References (8)

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2. C. Y. Lu, J. M. Sung, H. C. Kirsch, S. J. Hillenius, T. E. Smith, and L. Manchanda, "Anomalous C-V Characteristics of Implanted Poly MOS Structure in n+/p+ Dual-Gate CMOS Technology, " IEEE Electron Device Lett., Vol. 10, No. 5, pp. 192-194, 1989.
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4. S. W. Lee, C. Liang, C-S Pan, W. Lin, and J. Mark, "A Study on the Physical Mechanism in the Recovery of Gate Capacitance to Cox in Implanted Polysilicon MOS structures, " IEEE Electron Device Lett., Vol. 13, No. 1, pp. 2-4, 1992.
5. M. Jeng, P. Ko, and C. Hu, "A Deep-Submicrometer MOSFET Model For Analogmigital Circuit Simulations, " IEDM Tech. Dig., pp 114-1 17, 1988.
6. W. Lin and P. Chan, "Fix to Negative Output Conductance Problem in BSIM2 Model, " IEEE Trans. Electron Device, Vol. ED-40, pp. 1024-1028, 1993.
7. W. Lin, "A Circuit Simulation Model for Polysilicon Gate Depletion Effect in MOSFET, Part I-Theory and Implementation" Intel Internal Memo, Oct. 12, 1992.
8. B. Sheu, D. Scharfetter, P. KO, and M. Jeng, "BSIM: Berkeley Short-channel IGFET Model for MOS Transistors, " IEEE J. Solid-state Circuits, SC-22, No. 4, pp 558-566, 1987.