Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Integration, the VLSI Journal

Volumn 44, Issue 1, 2011, Pages 305-315

  Sun, Yang ^a   Cavallaro, Joseph R ^a  

^a Rice University   (United States)

Author keywords

3GPP LTE; ASIC; MAP decoder; QPP interleaver; Quadratic permutation polynomial; Turbo decoder; VLSI

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; HARDWARE; ITERATIVE DECODING; MEMORY ARCHITECTURE; MOBILE TELECOMMUNICATION SYSTEMS; POLYNOMIALS; THROUGHPUT; TURBO CODES; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS; ARCHITECTURE; CMOS INTEGRATED CIRCUITS; PARALLEL ARCHITECTURES;

3GPP-LTE; MAP DECODER; QPP INTERLEAVER; QUADRATIC PERMUTATION POLYNOMIALS; TURBO DECODERS; VLSI; 3GPP LTE; INTERLEAVERS;

PARALLEL ARCHITECTURES; TURBO CODES;

EID: 80055011925     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2010.07.001     Document Type: Article

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