Towards feasible implementations of low-latency multi-writer atomic registers

Proceedings - 2011 IEEE International Symposium on Network Computing and Applications, NCA 2011

Volumn , Issue , 2011, Pages 75-82

  Georgiou, Chryssis ^a   Nicolaou, Nicolas ^a,b   Russell, Alexander C ^b   Shvartsman, Alexander A ^b  

^a UNIVERSITY OF CYPRUS   (Cyprus)

^b UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

Approximation algorithms; Atomic memory; MWMR registers; NP Complete

Indexed keywords

ATOMIC MEMORIES; ATOMIC REGISTER; COMBINATORIAL PROBLEM; COMMUNICATION COST; COMPUTATION COSTS; COMPUTATIONAL BURDEN; COMPUTATIONAL FEASIBILITY; EXPERIMENTAL EVALUATION; FAST OPERATION; LOW LATENCY; MESSAGE PASSING SYSTEMS; MWMR REGISTERS; NP COMPLETE; QUORUM SYSTEMS; READ/WRITE REGISTERS; WRITE OPERATIONS;

ATOMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL EFFICIENCY; MESSAGE PASSING; POLYNOMIAL APPROXIMATION; WIRELESS SENSOR NETWORKS;

APPROXIMATION ALGORITHMS;

EID: 80054981913     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NCA.2011.18     Document Type: Conference Paper

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