Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 11, 2011, Pages 1677-1690

  Hanumaiah, Vinay ^a   Vrudhula, Sarma ^a   Chatha, Karam S ^a  

^a Arizona State University   (United States)

Author keywords

Convex optimization; dynamic voltage and frequency scaling; leakage dependence on temperature; makespan minimization; multi core; online thermal management; optimal control; performance optimization; task migration

Indexed keywords

DYNAMIC VOLTAGE AND FREQUENCY SCALING; MAKESPAN MINIMIZATION; MULTI CORE; OPTIMAL CONTROLS; PERFORMANCE OPTIMIZATIONS; TASK MIGRATION;

CONSTRAINED OPTIMIZATION; CONVEX OPTIMIZATION; INDUSTRIAL MANAGEMENT; SCHEDULING ALGORITHMS; SPACE RESEARCH;

TEMPERATURE CONTROL;

EID: 80054813906     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2161308     Document Type: Article

References (43)

1. S. Borkar, "Thousand core chips: A technology perspective," in Proc. DAC, 2007, pp. 746-749.
2. P. Chaparro, J. González, G. Magklis, Q. Cai, and A. González, "Understanding the thermal implications of multicore architectures," IEEE Trans. Parallel Distributed Syst., vol. 18, no. 8, pp. 1055-1065, Aug. 2007.
3. S. Zhang and K. S. Chatha, "Approximation algorithm for the temperature-aware scheduling problem," in Proc. ICCAD, 2007, pp. 281-288.
4. A. Cohen, F. Finkelstein, A. Mendelson, R. Ronen, and D. Rudoy, "On estimating optimal performance of CPU dynamic thermal management," IEEE Comput. Architecture Lett., vol. 2, no. 1, p. 6, Jan.-Dec. 2003.
5. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, "Temperature-aware microarchitecture: Modeling and implementation," ACM Trans. Arch. Code Opt., vol. 1, no. 1, pp. 94-125, 2004.
6. D. Brooks and M. Martonosi, "Dynamic thermal management for high performance microprocessors," in Proc. HPCA, 2001, pp. 171-182.
7. S. Cho and R. Melhem, "Corollaries to Amdahl's law for energy," IEEE Comput. Architecture Lett., vol. 7, no. 1, pp. 25-28, Jan. 2008.
8. J. Li and J. F. Martínez, "Power-performance considerations of parallel computing on chip multiprocessors," ACM Trans. Archit. Code Optim., vol. 2, no. 4, pp. 397-422, Dec. 2005.
9. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, and S. Ghosh, "HotSpot: A compact thermal modeling method for CMOS VLSI systems," IEEE Trans. Very Large Scale Integr. Syst., vol. 14, no. 5, pp. 501-513, May 2006.
10. P. Michaud and Y. Sazeides, "ATMI: An analytical model of temperature in microprocessors," in Proc. Workshop MOBS, 2007.
11. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proc. ISCA, 2000, pp. 83-94.
12. W. Liao, L. He, and K. M. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. Comput.-Aided Des., vol. 24, no. 7, pp. 1042-1053, Jul. 2005.
13. R. Mukherjee and S. O. Memik, "Physical aware frequency selection for dynamic thermal management in multi-core systems," in Proc. ICCAD, 2006, pp. 547-552.
14. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G. D. Micheli, "Temperature-aware processor frequency assignment for MPSoCs using convex optimization," in Proc. CODES, 2008, pp. 111-116.
15. R. Rao and S. Vrudhula, "Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors," in Proc. ICCAD, 2008, pp. 537-542.
16. T. Chantem, X. S. Hu, and R. P. Dick, "OnlineWork maximization under a peak temperature constraint," in Proc. ISLPED, 2009, pp. 105-110.
17. H. Jung and M. Pedram, "Stochastic dynamic thermal management: A Markovian decision-based approach," in Proc. ICCD, 2006, pp. 452-457.
18. V. Hanumaiah, S. Vrudhula, and K. S. Chatha, "Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control," in Proc. ICCAD, 2009, pp. 310-313.
19. K. Stavrou and P. Trancoso, "Thermal-aware scheduling for future chip multiprocessors," EURASIP J. Embedded Syst., vol. 2007, no. 1, p. 40, Jan. 2007.
20. A. Coskun, T. Rosing, and K. Gross, "Proactive temperature balancing for low cost thermal management in MPSoCs," in Proc. ICCAD, 2008, pp. 250-257.
21. A. Coskun, T. Rosing, K. Whisnant, and K. Gross, "Static and dynamic temperature-aware scheduling for multiprocessor SoCs," IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 9, pp. 1127-1140, Sep. 2008.
22. M. D. Powell, M. Gomaa, and T. N. Vijaykumar, "Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system," in Proc. ASPLOS, 2004, pp. 260-270.
23. F. Mulas, M. Pittau, M. Buttu, S. Carta, A. Acquaviva, L. Benini, and D. Atienza, "Thermal balancing policy for streaming computing on multiprocessor architectures," in Proc. DATE, 2008, pp. 734-739.
24. X. Zhou, J. Yang, M. Chrobak, and Y. Zhang, "Performance-aware thermal management via task scheduling," ACM Trans. Archit. Code Optim., vol. 7, no. 1, pp. 5:1-5:31, Apr. 2010.
25. S. Zhang and K. S. Chatha, "Thermal aware task sequencing on embedded processors," in Proc. DAC, 2010, pp. 585-590.
26. R. Jayaseelan and T. Mitra, "Temperature aware task sequencing and voltage scaling," in Proc. ICCAD, 2008, pp. 618-623.
27. V. Hanumaiah, S. Vrudhula, and K. S. Chatha, "Performance optimal speed control of multi-core processors under thermal constraints," in Proc. DATE, 2009, pp. 288-293.
28. Y. Wang, K. Ma, and X. Wang, "Temperature-constrained power control for chip multiprocessors with online model estimation," SIGARCH Comput. Archit. News, vol. 37, no. 3, pp. 314-324, Jun. 2009.
29. J. Donald and M. Martonosi, "Techniques for multicore thermal management: Classification and new exploration," in Proc. ISCA, 2006, pp. 78-88.
30. S. Heo, K. Barr, and K. Asanovic, "Reducing power density through activity migration," in Proc. ISLPED, 2003, pp. 217-222.
31. P. Michaud, A. Seznec, D. Fetis, Y. Sazeides, and T. Constantinou, "A study of thread migration in temperature-constrained multicores," ACM Trans. Arch. Code Opt., vol. 4, no. 2, pp. 9-1-9-28, Jun. 2007.
32. M. Hill and M. Marty, "Amdahl's law in the multicore era," Computer, vol. 41, no. 7, pp. 33-38, Jul. 2008.
33. W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron, "An improved block-based thermal model in hotspot 4.0 with granularity considerations," in Proc. WDDD, 2007.
34. K. Skadron, T. Abdelzaher, and M. R. Stan, "Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management," in Proc. HPCA, 2002, pp. 17-28.
35. D. E. Kirk, Optimal Control Theory. Englewood Cliffs, NJ: Prentice-Hall, 1970.
36. R. F. Hartl, S. P. Sethi, and R. G. Vickson, "A survey of the maximum principles for optimal control problems with state constraints," SIAM Rev., vol. 37, no. 2, pp. 181-218, 1995.
37. R. Rao and S. Vrudhula, "Fast and accurate prediction of the steady state throughput of multi-core processors under thermal constraints," IEEE Trans. Comput.-Aided Des., vol. 28, no. 10, pp. 1559-1572, Oct. 2009.
38. P. M. DeRusso, R. J. Roy, C. M. Close, and A. A. Desrochers, State Variables for Engineers. New York: Wiley-Interscience, 1997.
39. M. Monchiero, R. Canal, and A. González, "Power/performance/ thermal design space exploration for multicore architectures," IEEE Trans. Parallel Distributed Syst., vol. 19, no. 5, pp. 666-681, May 2008.
40. J. Munkres, "Algorithms for the assignment and transportation problems," J. Soc. Ind. Appl. Math., vol. 5, no. 1, pp. 32-38, 1957.
41. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in Proc. WWC, 2001, pp. 3-14.
42. V. Hanumaiah, R. Rao, and S. Vrudhula, The MAGMA Thermal Simulator. Tempe, AZ: Arizona State University [Online]. Available: http://vrudhula.lab. asu.edu/magma
43. S. P. Boyd and L. Vandenberghe, Convex Optimization. Cambridge, MA: Cambridge University Press, 2004.