Dynamic cache contention detection in multi-threaded applications

ACM SIGPLAN Notices

Volumn 46, Issue 7, 2011, Pages 27-37

  Zhao, Qin ^a   Koh, David ^a   Raza, Syed ^a   Amarasinghe, Saman ^a   Bruening, Derek ^b   Wong, Weng Fai ^c  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b GOOGLE INC   (United States)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Cache Contention; Dynamic Instrumentation; False Sharing; Shadow Memory

Indexed keywords

CACHE CONTENTION; CACHE SIMULATION; DATA SHARING; DIAGNOSTIC INFORMATION; DYNAMIC CACHE; DYNAMIC INSTRUMENTATION; FALSE SHARING; MANY CORE; MEMORY HIERARCHY; MULTI-CORE SYSTEMS; MULTI-THREADED APPLICATION; PERFORMANCE BOTTLENECKS; PERFORMANCE DEGRADATION; RUNTIME OVERHEADS; SHADOW MEMORIES; SHARING INFORMATION;

CACHE MEMORY; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 80053541916     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/2007477.1952688     Document Type: Article

References (40)

1. DynamoRIO dynamic instrumentation tool platform, Feb. 2009. http://dynamorio.org/.
2. E. Berger, K. McKinley, R. Blumofe, and P. Wilson. Hoard: A scalable memory allocator for multithreaded applications. ACM SIGPLAN Notices, 35(11):117-128, 2000. (Pubitemid 32470891)
3. P. W. Bolosky, W. J. Bolosky, and M. L. Scott. False sharing and its effect on shared memory. In In Proceedings of the USENIX Symposium on Experiences with Distributed and Multiprocessor Systems (SEDMS IV), pages 57-71, 1993.
4. D. Bruening. Efficient, Transparent, and Comprehensive Runtime Code Manipulation. PhD thesis, M.I.T., Sept. 2004.
5. M. Burrows, S. N. Freund, and J. L. Wiener. Run-time type checking for binary programs. In Proc. of the 12th International Conference on Compiler Construction (CC '03), pages 90-105, 2003.
6. J. M. Calandrino and J. H. Anderson. On the design and implementation of a cache-aware multicore real-time scheduler. Real-Time Systems, Euromicro Conference on, 0:194-204, 2009.
7. J. Carter, J. Bennett, and W. Zwaenepoel. Implementation and performance of Munin. In Proceedings of the thirteenth ACM symposium on Operating systems principles, page 164. ACM, 1991.
8. W. Cheng, Q. Zhao, B. Yu, and S. Hiroshige. Tainttrace: Efficient flow tracing with dynamic binary rewriting. In Proc. of the Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC '06), pages 749-754, 2006. (Pubitemid 47130300)
9. M. Dubois, J. Skeppstedt, L. Ricciulli, K. Ramamurthy, and P. Sten-strom. The detection and elimination of useless misses in multiprocessors. ACM SIGARCH Computer Architecture News, 21(2):88-97, 1993. (Pubitemid 23675569)
10. A. Fedorova. Operating system scheduling for chip multithreaded processors. PhD thesis, Harvard University, Cambridge, MA, USA, 2006.
11. V. W. Freeh. Dynamically controlling false sharing in distributed shared memory. International Symposium on High-Performance Distributed Computing, 0:403, 1996.
12. S. Gunther and J. Weidendorfer. Assessing cache false sharing effects by dynamic binary instrumentation. In Proceedings of the Workshop on Binary Instrumentation and Applications, pages 26-33. ACM, 2009.
13. J. J. Harrow. Runtime checking of multithreaded applications with visual threads. In Proc. of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification, pages 331-342, 2000.
14. Intel-Corporation. Intel Performance Tuning Utility 3.2. User Guide, Chapter 7.4.6.5, 2008.
15. A. Jaleel, R. S. Cohn, C.-K. Luk, and B. Jacob. CMP$im: A Pin-based on-the-fly multi-core cache simulator. In Proc. of the The Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), pages 28-36, Beijing, China, Jun 2008.
16. T. Jeremiassen and S. Eggers. Reducing false sharing on shared memory multiprocessors through compile time data transformations. ACM SIGPLAN Notices, 30(8):179-188, 1995.
17. Y. Ju and H. Dietz. Reduction of cache coherence overhead by compiler data layout and loop transformation. Languages and Compilers for Parallel Computing, pages 344-358, 1992.
18. V. Khera, P. R. LaRowe, Jr., and S. C. Ellis. An architecture-independent analysis of false sharing. Technical Report DUKE-TR-1993-13, Duke University, Durham, NC, USA, 1993.
19. S. Narayanasamy, C. Pereira, H. Patil, R. Cohn, and B. Calder. Automatic logging of operating system effects to guide application-level architecture simulation. In Proc. of the Joint International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS '06/Performance '06), pages 216-227, 2006. (Pubitemid 44619093)
20. N. Nethercote and A. Mycroft. Redux: A dynamic dataflow tracer. In Electronic Notes in Theoretical Computer Science, volume 89, 2003.
21. N. Nethercote and J. Seward. Valgrind: A framework for heavyweight dynamic binary instrumentation. In Proc. of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '07), pages 89-100, June 2007. (Pubitemid 47630678)
22. J. Newsome. Dynamic taint analysis for automatic detection, analysis, and signature generation of exploits on commodity software. In Proc. of the Network and Distributed System Security Symposium (NDSS 2005), 2005.
23. OpenWorks LLP. Helgrind: A data race detector, 2007. http://valgrind.org/ docs/manual/hg-manual.html/.
24. J. Peir and R. Cytron. Minimum distance: A method for partitioning recurrences for multiprocessors. IEEE Transactions on Computers, 38(8):1203-1211, 1989.
25. F. Qin, C. Wang, Z. Li, H.-S. Kim, Y. Zhou, and Y. Wu. Lift: A low-overhead practical information flow tracking system for detecting security attacks. In Proc. of the 39th International Symposium on Microarchitecture (MICRO 39), pages 135-148, 2006.
26. M. Rajagopalan, B. Lewis, and T. Anderson. Thread scheduling for multi-core platforms. In Proceedings of the 11th USENIX workshop on Hot topics in operating systems, pages 1-6. USENIX Association, 2007.
27. C. Ranger, R. Raghuraman, A. Penmetsa, G. Bradski, and C. Kozyrakis. Evaluating mapreduce for multi-core and multiprocessor systems. In Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pages 13-24, 2007. (Pubitemid 47208148)
28. Rational Software. Purify: Fast detection of memory leaks and access errors, 2000. http://www.rationalsoftware.com/products/whitepapers/319.jsp.
29. M. Ronsse, B. Stougie, J. Maebe, F. Cornelis, and K. D. Bosschere. An efficient data race detector backend for DIOTA. In Parallel Computing: Software Technology, Algorithms, Architectures & Applications, volume 13, pages 39-46. Elsevier, 2 2004.
30. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson. Eraser: a dynamic data race detector for multithreaded programs. ACM Trans. Comput. Syst., 15(4):391-411, 1997. (Pubitemid 127449840)
31. J. Seward and N. Nethercote. Using Valgrind to detect undefined value errors with bit-precision. In Proc. of the USENIX Annual Technical Conference, pages 2-2, 2005.
32. S. Sridharan, B. Keck, R. Murphy, S. Chandra, and P. Kogge. Thread migration to improve synchronization performance. In Workshop on Operating System Interference in High Performance Applications, 2006.
33. D. Tam, R. Azimi, and M. Stumm. Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors. In EuroSys '07: Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007, pages 47-58, New York, NY, USA, 2007. ACM. (Pubitemid 47281574)
34. J. Tao and W. Karl. CacheIn: A Toolset for Comprehensive Cache Inspection. Computational Science-ICCS 2005, pages 174-181, 2005. (Pubitemid 41348539)
35. J. Weidendorfer, M. Ott, T. Klug, and C. Trinitis. Latencies of conflicting writes on contemporary multicore architectures. Parallel Computing Technologies, pages 318-327, 2007.
36. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: characterization and methodological considerations. In Proc. of the 22nd International Symposium on Computer Architecture (ISCA '95), pages 24-36, 1995.
37. Q. Zhao, D. Bruening, and S. Amarasinghe. Efficient memory shadowing for 64-bit architectures. In Proc. of the The International Symposium on Memory Management (ISMM '10), Toronto, Canada, Jun 2010.
38. Q. Zhao, D. Bruening, and S. Amarasinghe. Umbra: Efficient and scalable memory shadowing. In Proc. of the International Symposium on Code Generation and Optimization (CGO '10), Apr. 2010.
39. Q. Zhao, R. Rabbah, S. Amarasinghe, L. Rudolph, and W.-F. Wong. Ubiquitous memory introspection. In International Symposium on Code Generation and Optimization, San Jose, CA, Mar 2007.
40. Q. Zhao, R. M. Rabbah, S. P. Amarasinghe, L. Rudolph, and W.-F. Wong. How to do a million watchpoints: Efficient debugging using dynamic instrumentation. In Proc. of the 17th International Conference on Compiler Construction (CC '08), pages 147-162, 2008.