PHAST: Hardware-accelerated shortest path trees

Proceedings - 25th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2011

Volumn , Issue , 2011, Pages 921-931

  Delling, Daniel ^a   Goldberg, Andrew V ^a   Nowatzyk, Andreas ^a   Werneck, Renato F ^a  

^a MICROSOFT RESEARCH   (United States)

Author keywords

GPU; high performance computing; route planning; shortest paths

Indexed keywords

BETWEENNESS; CENTRALITY MEASURES; CPU ARCHITECTURE; DIJKSTRA'S ALGORITHMS; GPU; GRAPH DIAMETER; HARDWARE-ACCELERATED; HIGH PERFORMANCE COMPUTING; INSTRUCTION-LEVEL; MULTI CORE; NOVEL ALGORITHM; PREPROCESSING PHASE; ROAD NETWORK; ROUTE PLANNING; SHORTEST PATH; SHORTEST PATH PROBLEM; SHORTEST PATH TREE; THREE ORDERS OF MAGNITUDE;

ALGORITHMS; COMPUTER SOFTWARE SELECTION AND EVALUATION; DISTRIBUTED PARAMETER NETWORKS; MOTOR TRANSPORTATION; ROADS AND STREETS; WIRELESS SENSOR NETWORKS;

TREES (MATHEMATICS);

EID: 80053265655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2011.89     Document Type: Conference Paper

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