Experimental demonstration of current mirrors based on silicon nanowire transistors for inversion and subthreshold operations

IEEE Transactions on Electron Devices

Volumn 58, Issue 10, 2011, Pages 3639-3642

  Huang, Ru ^a   Zou, Jibin ^a   Wang, Runsheng ^a   Fan, Chunhui ^a   Ai, Yujie ^a   Zhuge, Jing ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Analog and mixed signal application; current mirror (CM); silicon nanowire transistor (SNWT); subthreshold operation

Indexed keywords

ANALOG AND MIXED-SIGNAL INTEGRATED CIRCUIT; CURRENT MIRRORS; FIGURES OF MERITS; GATE-ALL-AROUND; LOW POWER APPLICATION; MATCHING ERROR; MIXED SIGNAL APPLICATIONS; OUTPUT RESISTANCE; OUTPUT VOLTAGES; SILICON NANOWIRE TRANSISTOR (SNWT); SILICON NANOWIRE TRANSISTORS; SUBTHRESHOLD OPERATION; SUBTHRESHOLD REGION;

DC POWER TRANSMISSION; ELECTRIC RESISTANCE; MIRRORS; NANOWIRES; THRESHOLD ELEMENTS; TRANSPORT PROPERTIES;

TRANSISTORS;

EID: 80053187927     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2162519     Document Type: Article

References (20)

1. L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, "Analog circuit design in nanoscale CMOS technologies," Proc. IEEE, vol. 97, no. 10, pp. 1687-1714, Oct. 2009.
2. International Technology Roadmap for Semiconductors (ITRS) 2009. [Online]. Available: http://public.itrs.net/
3. J. Wang, E. Polizzi, and M. Lundstrom, "A computational study of ballistic silicon nanowire transistors," in IEDM Tech. Dig., 2003, pp. 29.5.1-29.5.4.
4. R. Wang, H. Liu, R. Huang, J. Zhuge, L. Zhang, D.-W. Kim, X. Zhang, D. Park, and Y. Wang, "Experimental investigation on carrier transport in Si nanowire transistors: Ballistic efficiency and apparent mobility," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2960-2967, Nov. 2008.
5. J. Chen, T. Saraya, and T. Hiramoto, "Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range," in VLSI Symp. Tech. Dig., 2010, pp. 175-176.
6. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-performance fully depleted silicon nanowire (diameter = 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May 2006.
7. Y. Jiang, T. Y. Liow, N. Singh, L. H. Tan, G. Q. Lo, D. S. H. Chan, and D. L. Kwong, "Performance breakthrough in 8nm gate length gate-allaround nanowire transistors using metallic nanowire contacts," in VLSI Symp. Tech. Dig., 2008, pp. 34-35.
8. Y. Tian, R. Huang, Y. Q. Wang, J. Zhuge, R. Wang, J. Liu, X. Zhang, and Y. Wang, "New self-aligned silicon nanowire transistors on bulk substrate fabricated by epi-free compatible CMOS technology: Process integration, experimental characterization of carrier transport and low frequency noise," in IEDM Tech. Dig., 2007, pp. 895-898.
9. T. Ernst, L. Duraffourg, C. Dupré, E. Bernard, P. Andreucci, S. Bécu, E. Ollier, A. Hubert, C. Halté, J. Buckley, O. Thomas, G. Delapierre, S. Deleonibus, B. de Salvo, P. Robert, and O. Faynot, "Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?" in IEDM Tech. Dig., 2008, pp. 745-748.
10. M. Li, K. H. Yeo, S. D. Suk, Y. Y. Yeoh, D.-W. Kim, T. Y. Chung, K. S. Oh, and W.-S. Lee, "Sub-10nm gate-all-around CMOS nanowire transistor on bulk Si substrate," in VLSI Symp. Tech. Dig., 2009, pp. 94-95.
11. P. Hashemi, J. T. Teherani, and J. L. Hoyt, "Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal gate: Effects of hydrogen thermal annealing and nanowire shape," in IEDM Tech. Dig., 2010, pp. 34.5.1-34.5.4.
12. S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo, S. H. Kim, D. W. Kim, D. Park, and W. S. Lee, "TSNWFET for SRAM cell application: Performance variation and process dependency," in VLSI Symp. Tech. Dig., 2008, pp. 38-39.
13. S. Bangsaruntip, A. Majumdar, G. M. Cohen, S. U. Engelmann, Y. Zhang, M. Guillorn, L. M. Gignac, S. Mittal, W. S. Graham, E. A. Joseph, D. P. Klaus, J. Chang, E. A. Cartier, and J. W. Sleight, "Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm," in VLSI Symp. Tech. Dig., 2010, pp. 21-22.
14. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw Hill, 2001.
15. Z.Wang, "Analytical determination of output resistance and DC matching errors in MOS current mirrors," Proc. Inst. Elec. Eng.-Pt. G, Circuits, Devices Syst., vol. 137, no. 5, pp. 397-404, Oct. 1990.
16. J. Zhuge, R. Wang, R. Huang, X. Zhang, and Y. Wang, "Investigation of parasitic effects and design optimization in silicon nanowire MOSFETs for RF applications," IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2142-2147, Aug. 2008.
17. M. Saitoh, Y. Nakabayashi, H. Itokawa, M. Murano, I. Mizushima, K. Uchida, and T. Numata, "Short-channel performance and mobility analysis of (110)-and (100)-oriented tri-gate nanowire MOSFETs with raised source/drain extensions," in VLSI Symp. Tech. Dig., 2010, pp. 169-170.
18. B.-D. Yang, J.-S. Kim, J.-K. Lee, and J.-S. Lee, "A highly accurate BiCMOS cascode current mirror for wide output voltage range," in Proc. IEEE ISCAS, May 2008, pp. 2314-2317.
19. S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht, and A. Fish, "Digital subthreshold logic design-Motivation and challenges," in Proc. IEEE Int. Elect. Electron. Eng., Eilat, Israel, Dec. 2008, pp. 702-706.
20. A. Emira, E. Sanchez-Sinencio, and M. Schneider, "Design tradeoffs of CMOS current mirrors using one-equation for all-region model," in Proc. IEEE ISCAS, vol. 5, pp. 45-48.