Evaluation and improvements of programming models for the Intel SCC many-core processor

Proceedings of the 2011 International Conference on High Performance Computing and Simulation, HPCS 2011

Volumn , Issue , 2011, Pages 525-532

  Clauss, Carsten ^a   Lankes, Stefan ^a   Reble, Pablo ^a   Bemmerl, Thomas ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Many core Processors; Message Passing; MPI; Non Cache Coherent Shared Memory; RCCE; SCC

Indexed keywords

CACHE COHERENCE PROTOCOLS; CACHE COHERENCY; CHIP COMPLEXITY; EVALUATION AND IMPROVEMENT; MAIN MEMORY; MANY-CORE; MANY-CORE ARCHITECTURE; MPI; MULTI CORE; MULTI-CORE SYSTEMS; NON-COHERENT; PARALLEL PROCESSING; PROGRAMMING MODELS; RCCE; SCC; SHARED MEMORIES; SINGLE-CHIP;

CACHE MEMORY; CLOUD COMPUTING; CLUSTER COMPUTING; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE SELECTION AND EVALUATION; MEMORY ARCHITECTURE; MESSAGE PASSING;

MULTICORE PROGRAMMING;

EID: 80053032388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCSim.2011.5999870     Document Type: Conference Paper

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