-
1
-
-
77955076011
-
Memory miser: Improving main memory energy efficiency in servers
-
M. Tolentino, J. Turner, and K. Cameron, "Memory miser: Improving main memory energy efficiency in servers," IEEE Transactions on Computers, pp. 336-350, 2008.
-
(2008)
IEEE Transactions on Computers
, pp. 336-350
-
-
Tolentino, M.1
Turner, J.2
Cameron, K.3
-
2
-
-
79953071808
-
Mem-scale: Active low-power modes for main memory
-
Q. Deng, D. Meisner, L. Ramos, T. Wenisch, and R. Bianchini, "Mem-Scale: Active Low-Power Modes for Main Memory," in International Conference on Architectural Support for Programming Languages and Operating Systems, 2011.
-
(2011)
International Conference on Architectural Support for Programming Languages and Operating Systems
-
-
Deng, Q.1
Meisner, D.2
Ramos, L.3
Wenisch, T.4
Bianchini, R.5
-
3
-
-
67650783130
-
PowerNap: Eliminating server idle power
-
D. Meisner, B. Gold, and T. Wenisch, "PowerNap: eliminating server idle power," ACM SIGPLAN Notices, vol. 44, no. 3, pp. 205-216, 2009.
-
(2009)
ACM SIGPLAN Notices
, vol.44
, Issue.3
, pp. 205-216
-
-
Meisner, D.1
Gold, B.2
Wenisch, T.3
-
4
-
-
77952574782
-
Architecting for power management: The IBMR POWER7 approach
-
M. Ware, K. Rajamani, M. Floyd, B. Brock, J. Rubio, F. Rawson, and J. Carter, "Architecting for power management: The IBMR POWER7 approach," in HPCA, 2010, pp. 1-11.
-
(2010)
HPCA
, pp. 1-11
-
-
Ware, M.1
Rajamani, K.2
Floyd, M.3
Brock, B.4
Rubio, J.5
Rawson, F.6
Carter, J.7
-
5
-
-
80052709064
-
-
http://www.postgresql.org/, "PostgreSQL."
-
-
-
-
6
-
-
80052705744
-
-
http://osdldbt.sourceforge.net/, "Open Source Database Labs."
-
-
-
-
7
-
-
77952573046
-
Delay-Hiding energy management mechanisms for DRAM
-
M. Bi, R. Duan, and C. Gniady, "Delay-Hiding energy management mechanisms for DRAM," in International Symposium on High Performance Computer Architecture, 2010, pp. 1-10.
-
(2010)
International Symposium on High Performance Computer Architecture
, pp. 1-10
-
-
Bi, M.1
Duan, R.2
Gniady, C.3
-
8
-
-
70450273507
-
Scalable high performance main memory system using phase-change memory technology
-
M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in International Symposium on Computer Architecture, 2009, pp. 24-33.
-
(2009)
International Symposium on Computer Architecture
, pp. 24-33
-
-
Qureshi, M.K.1
Srinivasan, V.2
Rivers, J.A.3
-
9
-
-
80052764803
-
Memory sizing for server virtualization
-
Intel Corporation
-
S. Chahal and T. Glasgow, "Memory Sizing for Server Virtualization," in White Paper. Intel Corporation, 2007.
-
(2007)
White Paper
-
-
Chahal, S.1
Glasgow, T.2
-
11
-
-
0034442261
-
Power aware page allocation
-
A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis, "Power aware page allocation," ACM SIGOPS Operating Systems Review, vol. 34, no. 5, pp. 105-116, 2000. (Pubitemid 32470890)
-
(2000)
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
, pp. 105-116
-
-
Lebeck, A.R.1
Fan, X.2
Zeng, H.3
Ellis, C.4
-
12
-
-
0346003039
-
Design and implementation of poweraware virtual memory
-
H. Huang, P. Pillai, and K. Shin, "Design and Implementation of Poweraware Virtual Memory," in USENIX Annual Technical Conference, 2003, pp.5-16.
-
(2003)
USENIX Annual Technical Conference
, pp. 5-16
-
-
Huang, H.1
Pillai, P.2
Shin, K.3
-
13
-
-
80052753486
-
-
http://www.tpc.org, "Transaction Processing Council."
-
-
-
|