High performance graphene FETs with self-aligned buried gates fabricated on scalable patterned ni-catalyzed graphene

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 116-117

  Wang, Yanjie ^a   Huang, Bo Chao ^a   Zhang, Ming ^a   Miao, Congqin ^b   Xie, Ya Hong ^b   Woo, Jason C S ^a  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

buried gate; graphene; self aligned; transistor

Indexed keywords

BURIED GATES; FIELD-EFFECT MOBILITIES; GRAPHENE TRANSISTORS; HIGH QUALITY; ROOM TEMPERATURE MOBILITY; SELF-ALIGNED;

MESFET DEVICES; TRANSISTORS;

GRAPHENE;

EID: 80052688432     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. K. I. Bolotin et al., Solid State Communications, 146, 351, 2008.
2. J. S. Moonet al., Electron Device Letters, IEEE, 30, 650, 2009.
3. X. Li et al., Science, 324, 1312-13142009.
4. L. Liao et al., Proceedings of the National Academy of Sciences.
5. L. Liao et al., Nature, 467, 305.
6. Y. Wang et al., Electron Devices, IEEE Transactions on, 57, 12, 3472.
7. B.-C. Huang, et al., SSDM, 1036, 2010.
8. D. B. Farmer et al., Applied Physics Letters, 97
9. J. Zhu et al., Applied Physics Letters, 96, 19, 193503.