Suppression of VT variability degradation induced by NBTI with RDF control

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 150-151

  Tsunomura, T ^a   Nishimura, J ^b   Kumar, A ^b   Nishida, A ^a   Inaba, S ^a   Takeuchi, K ^a   Hiramoto, T ^a,b   Mogami, T ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Channel dopant; Halo; NBTI; VT variability

Indexed keywords

CHANNEL DOPANT; CHANNEL POTENTIAL; DOPANT CONCENTRATIONS; HALO; MATRIX ARRAYS; NBTI; NEGATIVE BIAS TEMPERATURE INSTABILITY; RANDOM DOPANT FLUCTUATION; SUPPRESSION MECHANISM;

INTEGRATED CIRCUIT TESTING;

DEGRADATION;

EID: 80052679435     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. N. Kimizuka, et al., VLSI Tech. Symp., 2000, p. 92.
2. S. Mahapatra et al., IEDM 2002, p. 505.
3. V. Huard et al., IEDM 2007, p. 797.
4. T. Grasser et al., IEDM, 2007, p. 801.
5. T. Grasser et al., IEDM, 2010, p. 82.
6. M. Agostinelli et al., IRPS 2005, p. 529.
7. H. Aono et al., IRPS, 2008, p. 67.
8. V. Huard et al., IRPS, 2008, p. 289.
9. B. Kaczer et al., IRPS, 2010, p. 26.
10. M. Denais, et al., IEDM, 2004, p. 109.
11. T. Hiramoto et al., MIRAI project mtg., 2010, p. 48.
12. M. Miyamura et al., IEDM, p. 447, 2008.
13. T. Tsunomura et al., VLSI Tech. Symp., p. 97, 2010.