A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 250-251

  Dighe, Saurabh ^a   Gupta, Sumeet ^b   De, Vivek ^a   Vangal, Sriram ^a   Borkar, Nitin ^a   Borkar, Shekhar ^a   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORE COMPUTATION; DYNAMIC VOLTAGE FREQUENCY SCALING; ENERGY BENEFITS; INDUSTRY-STANDARD BENCHMARKS; MAPPING SCHEME; OPERATING POINTS; OPERATIONAL FREQUENCY; REAL SYSTEMS; THERMAL VARIATION; WITHIN DIES;

ELECTRIC POTENTIAL; ENERGY EFFICIENCY; OPTIMIZATION; VOLTAGE REGULATORS;

VLSI CIRCUITS;

EID: 80052678519     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Howard et al., ISSCC, 2010 pp.108-109, 7-11 Feb. 2010
2. S. Dighe et al., ISSCC 2010 pp.174-175, 7-11 Feb. 2010
3. K. Bowman et al, ISSC 2001, pp.278-279, 2001
4. K. Kuhn, International CMOS Variability Conference, May 2009