On-chip combined C-V/I-V transistor characterization system in 45-nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 218-219

  Realov, Simeon ^a   Shepard, K L ^a  

^a Department of Earth and Environmental Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C-V MEASUREMENT; DEVICE ARRAYS; I-V AND C-V CHARACTERISTICS; INTRINSIC GATE CAPACITANCE; MEASUREMENT TECHNIQUES; ON CHIPS; ON-CHIP TRANSISTORS; QUASI-STATIC; RANDOM VARIABILITY;

CAPACITANCE; CAPACITANCE MEASUREMENT; CHARACTERIZATION; TRANSISTORS;

VLSI CIRCUITS;

EID: 80052668067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. L. Pang, et al, IEEE JSSC, pp. 2233-2243, Aug. 2009.
2. S. Chellappa, et al, Proc. DAC, pp. 771-716, 2010.
3. G. Zheng, et al, IEEE JSSC, pp. 3174-3192, Nov. 2009.
4. N. Arora and L. Song, IEEE EDL, pp. 92-94, Feb. 2004.
5. H. Zhao, et al, IEEE TED, pp. 1157-1159, May 2009.