A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz fT BiCMOS process

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 62-63

  Poulton, Ken ^a   Jewett, Bob ^a   Liu, Jacky ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

14 bit; BiCMOS; DAC; phase noise; R 2R; resampling; SFDR

Indexed keywords

14-BIT; BI-CMOS; DAC; R/2R; RESAMPLING; SFDR;

PHASE NOISE; SIGNAL GENERATORS;

VLSI CIRCUITS;

EID: 80052667582     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Bob Jewett, Jacky Liu, Ken Poulton, "A 1.2 GS/s 15b DAC for Precision Signal Generation", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp 110-111, Feb 2005