A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2011, Pages 70-71

  Lee, Keun Woo ^a   Choi, Se Kyoung ^a   Chung, Sung Jae ^a   Lee, Hye Lyoung ^a   Yi, Su Min ^a   Han, Byeong Il ^a   Lee, Byung In ^a   Lee, Dong Hwan ^a   Seo, Ji Hyun ^a   Park, Noh Yong ^a   Kim, Hae Soo ^a   Kim, Hyung Seok ^a   Youn, Tae Un ^a   Noh, Keum Hwan ^a   Lee, Min Kyu ^a   Lee, Ju Yeab ^a   Han, Kwang Hee ^a   Woo, Won Sic ^a   Cho, Seok Won ^a   Lee, Seung Cheol ^a   Kim, Sung Soon ^a   Hyun, Chan Sun ^a   Suh, Weon Joon ^a   Kim, Sang Deok ^a   Ahn, Myung Kyu ^a   Kim, Hyeon Soo ^a   Kim, Ki Seog ^a   Cho, Gyu Seog ^a   Park, Sung Kye ^a   Aritome, Seiichi ^a   Kim, Jin Woong ^a   Lee, Seok Kiu ^a   Hong, Sung Joo ^a   Park, Sung Wook ^a   more..

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AIR-GAPS; ARF IMMERSION LITHOGRAPHY; BIT LINES; DESIGN RULES; GATE ETCH; INTEGRATION TECHNOLOGIES; MULTI-LEVEL; NAND FLASH MEMORY; OPTIMIZED CONTROL; PATTERNING TECHNOLOGY; POLY DEPOSITION PROCESS; SCALING LIMITS; WORDLINES;

DYNAMIC RANDOM ACCESS STORAGE; NAND CIRCUITS; TECHNOLOGY;

FLASH MEMORY;

EID: 80052663498     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Prall, et al, IEDM 2010, pp.102-103.
2. C. Lee, et al, IEDM 2010, pp. 98-101.
3. K. T. Park et al., Jpn. J. Appl. Phys., Vol. 46, No. 4B, 2007.
4. K. N. Kim et al., Microelectronic Engineering 84, 2007, pp.1976.
5. Y. S. Kim, et al., IRPS 2010, pp.599.