Architecture for simultaneous coding and encryption using chaotic maps

Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Volumn , Issue , 2011, Pages 351-352

  Pande, Amit ^a   Zambreno, Joseph ^b   Mohapatra, Prasant ^a  

^a University of California   (United States)

^b Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC CODING; CHAOTIC MAP; CLOCK FREQUENCY; DECODER PERFORMANCE; FIXED POINT ARITHMETIC; HARDWARE IMPLEMENTATIONS;

COMPUTER ARCHITECTURE; HARDWARE; LYAPUNOV METHODS;

CHAOTIC SYSTEMS;

EID: 80052589525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2011.14     Document Type: Conference Paper

References (8)

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