Patterned electrode vertical field effect transistor: Theory and experiment

Journal of Applied Physics

Volumn 110, Issue 4, 2011, Pages

  Ben Sasson, Ariel J ^a   Tessler, Nir ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; BLOCK COPOLYMER LITHOGRAPHY; CURRENT MODULATION; DEVICE CHARACTERISTICS; DRAIN BIAS; ELECTRODE ARCHITECTURE; EXPERIMENTAL INVESTIGATIONS; ON/OFF CURRENT RATIO; PATTERNED ELECTRODE; SIMULATION RESULT; SPACE-CHARGE-LIMITED; UNDER GATE; VERTICAL CHANNELS;

ARCHITECTURE; BIAS VOLTAGE; BLOCK COPOLYMERS; COMPUTER SIMULATION; DRAIN CURRENT; FIELD EFFECT TRANSISTORS; MATHEMATICAL MODELS; PARAMETER EXTRACTION;

CURRENT VOLTAGE CHARACTERISTICS;

EID: 80052409844     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3622291     Document Type: Article

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