A power-aware task scheduling algorithm for application of DVS on multi-processor systems

IEEJ Transactions on Electronics, Information and Systems

Volumn 131, Issue 4, 2011, Pages 926-933

  Mori, Yuichiro ^a   Asakura, Koichi ^b   Watanabe, Toyohide ^a  

^a NAGOYA UNIVERSITY   (Japan)

^b DAIDO UNIVERSITY   (Japan)

Author keywords

Dynamic voltage scaling; Parallel processing; Power aware computing; Task scheduling

Indexed keywords

MULTITASKING; VOLTAGE STABILIZING CIRCUITS;

COMPLETION TIME; CRITICAL PATHS; DYNAMIC VOLTAGE SCALING; GREEDY METHOD; MAKESPAN; MULTIPROCESSOR-SYSTEM; PARALLEL PROCESSING; POWER-AWARE; POWER-AWARE COMPUTING; POWER-AWARE SCHEDULING; REDUCING POWER; TASK-SCHEDULING; TASK-SCHEDULING ALGORITHMS;

SCHEDULING ALGORITHMS;

EID: 80052329171     PISSN: 03854221     EISSN: 13488155     Source Type: Journal    
DOI: 10.1541/ieejeiss.131.926     Document Type: Article

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