Efficient deadlock detection for concurrent systems

9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011

Volumn , Issue , 2011, Pages 119-129

  Bensalem, Saddek ^a   Griesmayer, Andreas ^a,b   Legay, Axel ^c   Nguyen, Thanh Hung ^a   Peled, Doron ^d  

^a VERIMAG   (France)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c CAMPUS DE BEAULIEU   (France)

^d BAR ILAN UNIVERSITY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPONENT BASED SYSTEMS; CONCURRENT SYSTEMS; DEADLOCK DETECTION; INTERLEAVINGS; MEMORY FOOTPRINT; MODEL-CHECKING TECHNIQUES; POST PROCESSING; SHARED RESOURCES; STANDARD METHOD; STATE SPACE; VERIFICATION TECHNIQUES;

FORMAL METHODS; SPECIFICATIONS;

MODEL CHECKING;

EID: 80052132532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2011.5970518     Document Type: Conference Paper

References (35)

1. P. Godefroid and P. Wolper, "Using partial orders for the efficient verification of deadlock freedom and safety properties," FMSD, vol. 2, no. 2, pp. 149-164, 1993.
2. G. J. Holzmann, SPIN Model Checker, The: Primer and Reference Manual. Addison-Wesley, 2003.
3. D. Peled, "All from one, one for all: on model checking using representatives," in CAV. Springer-Verlag, 1993, pp. 409-423.
4. P. Wolper and P. Godefroid, "Partial-order methods for temporal verification," in CONCUR, ser. LNCS, vol. 715. Springer, 1993, pp. 233-246.
5. K. McMillan, Symbolic model checking. Kluwer Academic Publishers Norwell, MA, USA, 1993.
6. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu, "Symbolic model checking without BDDs," TACAS, pp. 193-207, 1999.
7. S. Bensalem, A. Griesmayer, A. Legay, T.-H. Nguyen, J. Sifakis, and R. Yan, "D-Finder 2: Towards efficient correctness of incremental design," in Nasa Formal Methods Symposium, 2011, to be published.
8. S. Bensalem, M. Bogza, A. Legay, T.-H. Nguyen, J. Sifakis, and R. Yan, "Incremental component-based construction and verification using invariants," in FMCAD, 2010.
9. R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. 35, no. 8, pp. 677- 691, 1986.
10. T. Ball, B. Cook, V. Levin, and S. K. Rajamani, "SLAM and static driver verifier: Technology transfer of formal methods inside Microsoft," in IFM, 2004.
11. P. A. Abdulla, Y.-F. Chen, G. Delzanno, F. Haziza, C.-D. Hong, and A. Rezine, "Constrained monotonic abstraction: A CEGAR for parameterized verification," in CONCUR, 2010, pp. 86-101.
12. A. Basu, M. Bozga, and J. Sifakis, "Modeling heterogeneous real-time components in BIP," in SEFM. IEEE Computer Society, 2006, pp. 3-12.
13. A. Basu, S. Bensalem, M. Gallien, F. Ingrand, C. Lesire, T.-H. Nguyen, and J. Sifakis, "Incremental component-based construction and verification of a robotic system," in ECAI, 2008.
14. S. Chaki, E. M. Clarke, J. Ouaknine, and N. Sharygina, "Automated, compositional and iterative deadlock detection," in MEMOCODE. IEEE, 2004, pp. 201-210. (Pubitemid 41718507)
15. C. Demartini, R. Iosif, and R. Sisto, "A deadlock detection tool for concurrent java programs," Softw., Pract. Exper., vol. 29, no. 7, pp. 577-603, 1999.
16. A. Cimatti, E. Clarke, F. Giunchiglia, and M. Roveri, "NuSMV: a new symbolic model checker," International Journal on Software Tools for Technology Transfer, vol. 2, pp. 410-425, 2000.
17. K. Ravi and F. Somenzi, "Hints to accelerate symbolic traversal," Correct Hardware Design and Verification Methods, pp. 639-673, 1999.
18. O. Grumberg, F. Lerda, O. Strichman, and M. Theobald, "Proof-guided underapproximation-widening for multiprocess systems," in ACM SIGPLAN Notices, vol. 40, no. 1. ACM, 2005, pp. 122-131.
19. D. Beyer, T. A. Henzinger, R. Jhala, and R. Majumdar, "The software model checker BLAST: Applications to software engineering," STTT, vol. 9, no. 5-6, pp. 505-525, 2007. (Pubitemid 47603660)
20. T. A. Henzinger, R. Jhala, R. Majumdar, and G. Sutre, "Lazy abstraction," in POPL. New York, NY, USA: ACM, 2002, pp. 58-70. [Online]. Available: http://doi.acm.org/10.1145/503272.503279 (Pubitemid 35009030)
21. "BIP," http://www-verimag.imag.fr/BIP,196.html?
22. S. Bliudze and J. Sifakis, "The algebra of connectors - structuring interaction in BIP," VERIMAG, Tech. Rep. TR-2007-3, 2007.
23. M. Bozga, M. Jaber, and J. Sifakis, "Source-to-source architecture transformation for performance optimization in bip," in SIES. IEEE, 2009, pp. 152-160.
24. S. Bensalem, A. Legay, T.-H. Nguyen, J. Sifakis, and R. Yan, "Incremental invariant generation for compositional design," in TASE, 2010, pp. 157-167.
25. S. Bensalem, M. Bozga, J. Sifakis, and T.-H. Nguyen, "Compositional verification for component-based systems and application," in ATVA, 2008, pp. 64-79.
26. S. Bensalem, M. Bozga, T.-H. Nguyen, and J. Sifakis, "DFinder: A tool for compositional deadlock detection and verification," in CAV, 2009, pp. 614-619.
27. S. Bensalem and Y. Lakhnech, "Automatic generation of invariants," FMSD, vol. 15, no. 1, pp. 75-92, 1999.
28. J. Sifakis, "Structural properties of Petri nets," Mathematical Foundations of Computer Science 1978, pp. 474-483, 1978.
29. J. Whaley, "JavaBDD java binary decision diagram library," http://javabdd.sourceforge.net/. [Online]. Available: http:// javabdd.sourceforge.net/
30. A. Hu and D. Dill, "Reducing BDD size by exploiting functional dependencies," in DAC. ACM, 1993, pp. 266- 271. (Pubitemid 23673252)
31. S. Tani, K. Hamaguchi, and S. Yajima, "The complexity of the optimal variable ordering problems of shared binary decision diagrams," Algorithms and Computation, pp. 389-398, 1993.
32. O. Coudert, J. Madre, and C. Berthet, "Verifying temporal properties of sequential machines without building their state diagrams," in CAV, 1991, pp. 23-32.
33. "D-Finder tool," available at http://www-verimag.imag.fr/ DFinder.
34. D. Heimbold and D. Luckham, "Debugging Ada tasking programs," IEEE Softw., vol. 2, no. 2, pp. 47-57, 1985.
35. A. Hu, G. York, and D. Dill, "New techniques for efficient verification with implicitly conjoined BDDs," in Annual ACM IEEE Design Automation Conference: Proceedings of the 31 st annual conference on Design automation. Association for Computing Machinery, Inc, One Astor Plaza, 1515 Broadway, New York, NY, 10036-5701, USA, 1994.