Model-driven system validation by scenarios

Lecture Notes in Electrical Engineering

Volumn 36 LNEE, Issue , 2009, Pages 57-69

  Carioni, A ^b   Gargantini, A ^b   Riccobene, E ^a   Scandurra, P ^b  

^a UNIVERSITY OF MILAN   (Italy)

^b NONE

Author keywords

Abstract state machines; Model based design; System validation; UML

Indexed keywords

ABSTRACT STATE MACHINES; CO-DESIGN ENVIRONMENTS; FORMAL MODEL; GRAPHICAL MODEL; LEVELS OF ABSTRACTION; MODEL DRIVEN DESIGN; MODEL TRANSFORMATION; MODEL VALIDATION; MODEL-BASED DESIGN; MODEL-DRIVEN; SYSTEM COMPONENTS; SYSTEM VALIDATION; SYSTEMC; UML; UML DESIGN; UML MODEL; UML PROFILES; VALIDATION APPROACH; VALIDATION TOOLS;

ABSTRACTING; LOGIC DESIGN; SYSTEMS ANALYSIS; UNIFIED MODELING LANGUAGE;

EMBEDDED SYSTEMS;

EID: 80051778840     PISSN: 18761100     EISSN: 18761119     Source Type: Book Series    
DOI: 10.1007/978-1-4020-9714-0_4     Document Type: Article

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