A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 69-72

  Kim, Daeyeon ^a   Chen, Gregory ^a   Fojtik, Matthew ^a   Seok, Mingoo ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE MODE; BITCELL; CMOS PROCESSS; LEAKAGE POWER CONSUMPTION; LOW LEAKAGE; LOW VOLTAGES; OPERATION SPEED; ROBUST OPERATION; SECONDARY SUPPLIES; SENSOR APPLICATIONS; SPEED COMPENSATION; SRAM CELL;

CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 79960878479     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5937503     Document Type: Conference Paper

References (8)

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