A combinational digital logic approach to STDP

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 673-676

  Cassidy, Andrew ^a   Andreou, Andreas G ^a   Georgiou, Julius ^b  

^a Johns Hopkins University   (United States)

^b UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL LOGIC; DIGITAL LOGIC GATES; EXCITATION EXPERIMENTS; HEBBIAN; LOW COMPLEXITY; SPIKE TIMING; SPIKING NEURAL NETWORKS; SYNAPTIC WEIGHT; UNSUPERVISED TRAINING;

DIGITAL CIRCUITS; LOGIC GATES; NEURAL NETWORKS; TIMING CIRCUITS;

LOGIC CIRCUITS;

EID: 79960868281     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5937655     Document Type: Conference Paper

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