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Volumn 46, Issue 8, 2011, Pages 1940-1951

Fully-integrated on-chip DC-DC converter with a 450X output range

Author keywords

Dynamic voltage scaling; frequency scaling; fully integrated DC DC converter; switch scaling; wide output power range

Indexed keywords

DYNAMIC VOLTAGE SCALING; FREQUENCY SCALING; FULLY-INTEGRATED DC-DC CONVERTER; OUTPUT POWER; SWITCH SCALING;

EID: 79960842478     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2157253     Document Type: Conference Paper
Times cited : (96)

References (20)
  • 5
    • 36949001469 scopus 로고    scopus 로고
    • An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget
    • DOI 10.1109/MICRO.2006.8, 4041859, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
    • C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An analysis of efficientmulti-core global powermanagement policies: Maximizing performance for a given power budget," in 39th Annu. IEEE/ACM Int. Symp. Microarchitecture, 2006, pp. 347-358. (Pubitemid 351337009)
    • (2006) Proceedings of the Annual International Symposium on Microarchitecture, MICRO , pp. 347-358
    • Isci, C.1    Buyuktosunoglu, A.2    Cher, C.-Y.3    Bose, P.4    Martonosi, M.5
  • 6
    • 77957986724 scopus 로고    scopus 로고
    • Power reduction schemes in next generation Intel® ATOM™ processor based SOC for handheld applications
    • R. Islam, A. Sabbavarapu, and R. Patel, "Power reduction schemes in next generation Intel® ATOM™ processor based SOC for handheld applications," in IEEE Symp. VLSI Circuits, 2010, pp. 173-174.
    • (2010) IEEE Symp. VLSI Circuits , pp. 173-174
    • Islam, R.1    Sabbavarapu, A.2    Patel, R.3
  • 7
    • 41549111045 scopus 로고    scopus 로고
    • A high efficiency DC-DC converter using 2 nHintegrated inductors
    • Aug.
    • J. Wibben and R. Harjani, "A high efficiency DC-DC converter using 2 nHintegrated inductors," IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 844-854, Aug. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.8 , pp. 844-854
    • Wibben, J.1    Harjani, R.2
  • 9
    • 31344455697 scopus 로고    scopus 로고
    • Ultra-Dynamic Voltage scaling (UDVS) using sub-threshold operation and local voltage dithering
    • DOI 10.1109/JSSC.2005.859886
    • B. Calhoun and A. P. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238-245, Jan. 2006. (Pubitemid 43145981)
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.1 , pp. 238-245
    • Calhoun, B.H.1    Chandrakasan, A.P.2
  • 10
    • 77649112185 scopus 로고    scopus 로고
    • An ultra-lowenergy multi-standard JPEG co-processor in 65 nm CMOS with sub/ near threshold supply voltage
    • Mar.
    • Y. Pu, J. Pineda de Gyvez, H. Corporaal, and Y. Ha, "An ultra-lowenergy multi-standard JPEG co-processor in 65 nm CMOS with sub/ near threshold supply voltage," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 668-680, Mar. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.3 , pp. 668-680
    • Pu, Y.1    Pineda De Gyvez, J.2    Corporaal, H.3    Ha, Y.4
  • 11
    • 59349118349 scopus 로고    scopus 로고
    • A 32 kb 10 T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
    • Feb.
    • I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10 T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.2 , pp. 650-658
    • Chang, I.J.1    Kim, J.-J.2    Park, S.P.3    Roy, K.4
  • 12
    • 0035023759 scopus 로고    scopus 로고
    • Capacitive voltage multipliers: A high efficiency method to generate multiple on-chip supply voltages
    • R. Balczewski and R. Harjani, "Capacitive voltage multipliers: A high efficiency method to generate multiple on-chip supply voltages," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2001, pp. 508-511. (Pubitemid 32470110)
    • (2001) Proceedings - IEEE International Symposium on Circuits and Systems , vol.1 , pp. 508-511
    • Balczewski, R.1    Harjani, R.2
  • 14
    • 33847725765 scopus 로고    scopus 로고
    • Optimization of CMOS transistors for low power DC-DC converters
    • DOI 10.1109/PESC.2005.1581930, 1581930, 36th IEEE Power Electronics Specialists Conference 2005
    • S. Musunuri and P. L. Chapman, "Optimization of CMOS transistors for low power DC-DC converters," in Proc. IEEE 36th Power Electronics Specialists Conf., 2005, pp. 2151-2157. (Pubitemid 46379475)
    • (2005) PESC Record - IEEE Annual Power Electronics Specialists Conference , vol.2005 , pp. 2151-2157
    • Musunuri, S.1    Chapman, P.L.2
  • 15
    • 0742268980 scopus 로고    scopus 로고
    • An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction
    • Jan.
    • D. Ma, W.-H. Ki, and C.-Y. Tsui, "An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 140-149, Jan. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.1 , pp. 140-149
    • Ma, D.1    Ki, W.-H.2    Tsui, C.-Y.3
  • 16
    • 10444287609 scopus 로고    scopus 로고
    • A 4 A quiescent- current dual-mode digitally controlled buck converter IC for cellular phone applications
    • Dec.
    • J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, "A 4 A quiescent- current dual-mode digitally controlled buck converter IC for cellular phone applications," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2342-2348, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2342-2348
    • Xiao, J.1    Peterchev, A.V.2    Zhang, J.3    Sanders, S.R.4
  • 18
    • 78649843074 scopus 로고    scopus 로고
    • [Online]. Available:
    • MOSIS Wafer Acceptance Tests [Online]. Available: http:// www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ibm-013/ v02b-8rf-8lm-dm-params. txt
    • MOSIS Wafer Acceptance Tests
  • 19
    • 36349026369 scopus 로고    scopus 로고
    • A multistage interleaved synchronous buck converter with integrated output filter in 0.18 μm SiGe process
    • DOI 10.1109/TPEL.2007.909288
    • S. Abedinpour, B. Bakkaloglu, and S. Kiaei, "A multistage interleaved synchronous buck converter with integrated output filter in 0.18 m SiGe process," IEEE Trans. Power Electron., pp. 2164-2175, Nov. 2007. (Pubitemid 350154050)
    • (2007) IEEE Transactions on Power Electronics , vol.22 , Issue.6 , pp. 2164-2175
    • Abedinpour, S.1    Bakkaloglu, B.2    Kiaei, S.3
  • 20
    • 79955727298 scopus 로고    scopus 로고
    • 20 A to 100 mA DC-DC converter with 2.8 V to 4.2 V battery supply for portable applications in 45 nm cmos
    • S. Bandyopadhyay, Y. Ramadass, and A. P. Chandrakasan, "20 A to 100 mA DC-DC converter with 2.8 V to 4.2 V battery supply for portable applications in 45 nm cmos," in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 386-387.
    • (2011) IEEE ISSCC Dig. Tech. Papers , pp. 386-387
    • Bandyopadhyay, S.1    Ramadass, Y.2    Chandrakasan, A.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.