Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors

Proceedings - IEEE International SOC Conference, SOCC 2010

Volumn , Issue , 2010, Pages 15-18

  Köse, Selçuk ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGNS; COMPUTATIONALLY EFFICIENT; DECOUPLING CAPACITOR; DESIGN METHODOLOGY; NEW DESIGN; ON CHIPS; ON-CHIP VOLTAGE REGULATOR; POWER DELIVERY NETWORK; POWER DISTRIBUTION NETWORK; POWER SUPPLY; POWER-SUPPLY NOISE;

DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ELECTRIC POWER TRANSMISSION; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEMS ANALYSIS; VOLTAGE REGULATORS;

CAPACITORS;

EID: 79960734452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2010.5784662     Document Type: Conference Paper

References (9)

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6. L. Smith et al., "Power Distribution System Design Methodology and Capacitor Selection for Modem CMOS Technology," IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, pp. 284-291, August 1999. (Pubitemid 30559648)
7. E. Salman, E. G. Friedman, R. M. Secerenau, and O. L. Martin, "Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 56, No. 5, pp. 997-1004, May 2009.
8. A. Todri, M. Marek-Sadowska, F. Maire, and C. Matheron, "A Study of Decoupling Capacitor Effectiveness in Power and Ground Grid Networks," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 653-658, March 2009.
9. G. Venezian, "On the Resistance between Two Points on a Grid," American Journal of P hysics, Vol. 62, No. 11, pp. 1000-1004, November 1994