CPPC: Correctable parity protected cache

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 223-234

  Manoochehri, Mehrtash ^a   Annavaram, Murali ^a   Dubois, Michel ^a  

^a University of Southern California ^*  (United States)

Author keywords

Cache; Parity; Reliability

Indexed keywords

CACHE; DEGREE OF RELIABILITY; DIRTY DATA; ERROR CORRECTING CODE; ERROR CORRECTION CAPABILITY; MULTI-BITS; PARITY; SHRINKING FEATURE SIZES; SIMULATION RESULT; SOFT ERROR; WRITE-BACK;

ERROR CORRECTION; ERROR DETECTION; MICROPROCESSOR CHIPS; RELIABILITY; TWO DIMENSIONAL; COMPUTER ARCHITECTURE;

COMPUTER ARCHITECTURE; ERROR CORRECTION;

EID: 79960164462     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000091     Document Type: Conference Paper

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