Reduction of FPGA resources for regular expression matching by relation similarity

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Volumn , Issue , 2011, Pages 401-402

  Košař, Vlastimil ^a   Kořenek, Jan ^a  

^a BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

INTRUSION DETECTION SYSTEMS; LOOK UP TABLE; MALICIOUS TRAFFIC; MULTI-GIGABIT NETWORKS; NONDETERMINISTIC FINITE AUTOMATON; NUMBER OF STATE; REGULAR EXPRESSIONS; REGULAR-EXPRESSION MATCHING;

FINITE AUTOMATA; FORMAL METHODS; NETWORKS (CIRCUITS); PATTERN MATCHING; TABLE LOOKUP;

INTRUSION DETECTION;

EID: 79959959380     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2011.5783121     Document Type: Conference Paper

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