-
3
-
-
0025553145
-
Feedforward compensation techniques for high-frequency CMOS amplifiers
-
DOI 10.1109/4.62197
-
W. Sansen and Z. Y. Chang, "Feedforward compensation techniques for high-frequency CMOS amplifiers& (Pubitemid 21738762)
-
(1990)
IEEE Journal of Solid-State Circuits
, vol.25
, Issue.6
, pp. 1590-1595
-
-
Sansen Willy1
Chang, Z.Y.2
-
4
-
-
0026982485
-
A 100 MHz 100 dB operational amplifier with multipath nested Miller compensation structure
-
Dec
-
R. G. H. Eschauzier, L. P. T. Kerklaan, and J. H. Huijsing, "A 100 MHz 100 dB operational amplifier with multipath nested Miller compensation structure", IEEE J. Solid-State Circuits, vol. 27, pp. 1709-1717, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1709-1717
-
-
Eschauzier, R.G.H.1
Kerklaan, L.P.T.2
Huijsing, J.H.3
-
5
-
-
0035441319
-
Analysis of multistage amplifier-frequency compensation
-
DOI 10.1109/81.948432, PII S1057712201077169
-
K. N. Leung and P. K. T. Mok, "Analysis of multistage amplifier - frequency compensation", IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, pp. 1041-1056, Sep. 2001. (Pubitemid 32981624)
-
(2001)
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
, vol.48
, Issue.9
, pp. 1041-1056
-
-
Leung, K.N.1
Mok, P.K.T.2
-
6
-
-
34547120455
-
Advances in reversed nested Miller compensation
-
DOI 10.1109/TCSI.2007.900170, Transactions on Circuits and Systems I: Regular Papers, IEEE Transactions on [Circuits and Systems I: Fundamental Theory and Applications, IEEE
-
A. D. Grasso, G. Palumbo, and S. Pennisi, "Advances in reversed nested Miller compensation", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp. 1459-1470, Jul. 2007. (Pubitemid 47104012)
-
(2007)
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol.54
, Issue.7
, pp. 1459-1470
-
-
Grasso, A.D.1
Palumbo, G.2
Pennisi, S.3
-
7
-
-
0026107482
-
Two novel fully complementary self-biased CMOS differential amplifiers
-
Feb
-
M. Bazes, "Two novel fully complementary self-biased CMOS differential amplifiers", IEEE J. Solid-State Circuits, vol. 26, pp. 165-168, Feb. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 165-168
-
-
Bazes, M.1
-
8
-
-
33750841997
-
Design of a sub-mW 960-MHz UWB CMOS LNA
-
DOI 10.1109/JSSC.2006.883321, 1717668
-
S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, "Design of a sub-mW 960-MHz UWB CMOS LNA", IEEE J. Solid-State Circuits, vol. 41, pp. 2449-2456, Nov. 2006. (Pubitemid 44711602)
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.11
, pp. 2449-2456
-
-
Wang, S.B.T.1
Niknejad, A.M.2
Brodersen, R.W.3
-
9
-
-
0035247388
-
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
-
DOI 10.1109/4.902767, PII S0018920001009313
-
C.-Y. Yang and S.-I. Liu, "A one-wire approach for skew-compensating clock distribution based on bidirectional techniques", IEEE J. Solid-State Circuits, vol. 36, pp. 266-272, Feb. 2001. (Pubitemid 32296953)
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.2
, pp. 266-272
-
-
Yang, C.-Y.1
Liu, S.-I.2
-
10
-
-
0030784364
-
A self-biased high performance folded cascode CMOS Op-amp
-
Jan. 4-7
-
P. Mandal and V. Visvanathan, "A self-biased high performance folded cascode CMOS Op-amp", in Proc. 10th Int. Conf. VLSI Design, Jan. 4-7, 1997, pp. 429-434.
-
(1997)
Proc. 10th Int. Conf. VLSI Design
, pp. 429-434
-
-
Mandal, P.1
Visvanathan, V.2
-
11
-
-
77955995395
-
Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency
-
May 30-Jun. 2
-
M. Figueiredo, E. Santin, J. Goes, R. Santos-Tavares, and G. Evans, "Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency", in Proc. IEEE Int. Symp. Circuits Syst., May 30-Jun. 2 2010, pp. 2828-2831.
-
(2010)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 2828-2831
-
-
Figueiredo, M.1
Santin, E.2
Goes, J.3
Santos-Tavares, R.4
Evans, G.5
-
12
-
-
0031344829
-
Compact high gain CMOS Op amp design using comparators
-
Aug. 3-6
-
J. Purcell and H. S. Abdel-Aty-Zohdy, "Compact high gain CMOS Op amp design using comparators", in Proc. 40th Midwest Symp. Circuits Syst., Aug. 3-6, 1997, vol. 2, pp. 1050-1052.
-
(1997)
Proc. 40th Midwest Symp. Circuits Syst.
, vol.2
, pp. 1050-1052
-
-
Purcell, J.1
Abdel-Aty-Zohdy, H.S.2
-
13
-
-
0020906580
-
An improved frequency compensation technique for CMOS operational amplifiers
-
Dec
-
B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers", IEEE J. Solid-State Circuits, vol. 18, pp. 629-633, Dec. 1983.
-
(1983)
IEEE J. Solid-State Circuits
, vol.18
, pp. 629-633
-
-
Ahuja, B.K.1
-
14
-
-
57949102581
-
Comparison of the frequency compensation techniques for CMOS two-stage Miller OTAs
-
Nov
-
A. D. Grasso, G. Palumbo, and S. Pennisi, "Comparison of the frequency compensation techniques for CMOS two-stage Miller OTAs", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, pp. 1099-1103, Nov. 2008.
-
(2008)
IEEE Trans. Circuits Syst. II, Exp. Briefs.
, vol.55
, pp. 1099-1103
-
-
Grasso, A.D.1
Palumbo, G.2
Pennisi, S.3
-
15
-
-
0346707501
-
Analysis of switched-capacitor commonmode feedback circuit
-
Dec
-
O. Choksi and L. R. Carley, "Analysis of switched-capacitor commonmode feedback circuit", IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, pp. 906-917, Dec. 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.50
, pp. 906-917
-
-
Choksi, O.1
Carley, L.R.2
-
16
-
-
79959785473
-
-
Online. Available
-
MATLAB, [Online]. Available: http://www.mathworks.com
-
-
-
-
17
-
-
0031381291
-
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps
-
Nov
-
F. Leyn, W. Daems, G. Gielen, and W. Sansen, "A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps", in CAD Dig. Tech. Papers, Nov. 1997, pp. 374-381.
-
(1997)
CAD Dig. Tech. Papers.
, pp. 374-381
-
-
Leyn, F.1
Daems, W.2
Gielen, G.3
Sansen, W.4
-
18
-
-
77953478121
-
Generalized time-and transfer-constant circuit analysis
-
Jun
-
A. Hajimiri, "Generalized time-and transfer-constant circuit analysis", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, pp. 1105-1121, Jun. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.57
, pp. 1105-1121
-
-
Hajimiri, A.1
-
19
-
-
77953478588
-
The design of fast-settling three-stage amplifiers using the open-loop damping factor as a design parameter
-
Jun
-
R. Nguyen and B. Murmann, "The design of fast-settling three-stage amplifiers using the open-loop damping factor as a design parameter", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, pp. 1244-1254, Jun. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.57
, pp. 1244-1254
-
-
Nguyen, R.1
Murmann, B.2
-
20
-
-
28444478100
-
Design-oriented estimation of thermal noise in switched-capacitor circuits
-
DOI 10.1109/TCSI.2005.853909
-
R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, "Design-oriented estimation of thermal noise in switched-capacitor circuits", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, pp. 2358-2368, Nov. 2005. (Pubitemid 41723950)
-
(2005)
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol.52
, Issue.11
, pp. 2358-2368
-
-
Schreier, R.1
Silva, J.2
Steensgaard, J.3
Temes, G.C.4
-
21
-
-
38649137688
-
Noise characterization of 130 nm and 90 nm CMOS technologies for analog front-end electronics
-
Oct. 29-Nov. 1
-
M. Manghisoni, L. Ratti, V. Re, V. Speziali, and G. Traversi, "Noise characterization of 130 nm and 90 nm CMOS technologies for analog front-end electronics", in IEEE Nucl. Sci. Symp. Conf. Rec, Oct. 29-Nov. 1 2006, vol. 1, pp. 214-218.
-
(2006)
IEEE Nucl. Sci. Symp. Conf. Rec.
, vol.1
, pp. 214-218
-
-
Manghisoni, M.1
Ratti, L.2
Re, V.3
Speziali, V.4
Traversi, G.5
-
22
-
-
1842832730
-
Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors
-
K. W. Chew, K. S. Yeo, and S.-F. Chu, "Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors", Solid-State Electron., vol. 48, no. 7, pp. 1101-1109, 2004.
-
(2004)
Solid-State Electron.
, vol.48
, Issue.7
, pp. 1101-1109
-
-
Chew, K.W.1
Yeo, K.S.2
Chu, S.-F.3
-
25
-
-
70249126615
-
The recycling folded cascode: A general enhancement of the folded cascode amplifier
-
Sep
-
R. S. Assaad and J. Silva-Martinez, "The recycling folded cascode: A general enhancement of the folded cascode amplifier", IEEE J. Solid-State Circuits, vol. 44, pp. 2535-2542, Sep. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, pp. 2535-2542
-
-
Assaad, R.S.1
Silva-Martinez, J.2
-
26
-
-
33947574144
-
High-drive and linear CMOS class-AB pseudo-differential amplifier
-
DOI 10.1109/TCSII.2006.886239
-
G. Giustolisi, A. D. Grasso, and S. Pennisi, "High-drive and linear CMOS Class-AB pseudo-differential amplifier", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp. 112-116, Feb. 2007. (Pubitemid 46477673)
-
(2007)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.54
, Issue.2
, pp. 112-116
-
-
Giustolisi, G.1
Grasso, A.D.2
Pennisi, S.3
-
27
-
-
0025384745
-
A CMOS large-swing low-distortion three-stage class AB power amplifier
-
Feb
-
F. N. L. O. Eynde, P. F. M. Ampe, L. Verdeyen, and W. M. C. Sansen, "A CMOS large-swing low-distortion three-stage class AB power amplifier", IEEE J. Solid-State Circuits, vol. 25, pp. 265-273, Feb. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 265-273
-
-
Eynde, F.N.L.O.1
Ampe, P.F.M.2
Verdeyen, L.3
Sansen, W.M.C.4
-
28
-
-
4344654053
-
Power efficient fully differential low-voltage two stage class AB/AB Op-amp architectures
-
May 23-26
-
S. Thoutam, J. Ramirez-Angulo, A. Lopez-Martin, and R. G. Carvajal, "Power efficient fully differential low-voltage two stage class AB/AB Op-amp architectures", in IEEE Proc. Int. Symp. Circuits Syst., May 23-26, 2004, vol. 1, pp. I-733-I-736.
-
(2004)
IEEE Proc. Int. Symp. Circuits Syst.
, vol.1
-
-
Thoutam, S.1
Ramirez-Angulo, J.2
Lopez-Martin, A.3
Carvajal, R.G.4
-
29
-
-
51749112891
-
Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm
-
May 18-21
-
R. Santos-Tavares, N. Paulino, J. Higino, J. Goes, and J. P. Oliveira, "Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm", in Proc. IEEE Int. Symp. Circuits Syst., May 18-21, 2008, pp. 724-727.
-
(2008)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 724-727
-
-
Santos-Tavares, R.1
Paulino, N.2
Higino, J.3
Goes, J.4
Oliveira, J.P.5
-
30
-
-
79959787668
-
-
Online. Available
-
Texas Instruments, [Online]. Available: http://focus.ti.com/docs/prod/ folders/print/ths4521.html
-
-
-
-
31
-
-
77956003000
-
Very low-voltage, low-power and fast-settling OTA for switched-capacitor applications
-
Dec
-
M. Yavari and O. Shoaei, "Very low-voltage, low-power and fast-settling OTA for switched-capacitor applications", in Proc. 14th Int. Conf. Microelectron., Dec. 2002, pp. 10-13.
-
(2002)
Proc. 14th Int. Conf. Microelectron.
, pp. 10-13
-
-
Yavari, M.1
Shoaei, O.2
-
32
-
-
70350453751
-
Slew-rate and gain enhancement in two stage operational amplifiers
-
May
-
A. P. Perez, K. Y. B. Nithin, E. Bonizzoni, and F. Maloberti, "Slew-rate and gain enhancement in two stage operational amplifiers", in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp. 2485-2488.
-
(2009)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 2485-2488
-
-
Perez, A.P.1
Nithin, K.Y.B.2
Bonizzoni, E.3
Maloberti, F.4
-
33
-
-
33644994835
-
A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications
-
Mar
-
M. M. Ahmadi, "A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 169-173, Mar. 2006.
-
(2006)
IEEE Trans. Circuits Syst. II, Exp. Briefs.
, vol.53
, pp. 169-173
-
-
Ahmadi, M.M.1
|