Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2011, Pages 134-139

  Datta, Rudrajit ^a   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ERROR; DATA BITS; EFFECTIVE SIZE; ERROR CORRECTION CODES; MAIN MEMORY; MEMORY SYSTEMS; MULTI-BIT ERROR; READ OPERATION;

CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION;

PHASE CHANGE MEMORY;

EID: 79959659795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2011.5783773     Document Type: Conference Paper

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