Three-dimensional (3D) integration technology

ECS Transactions

Volumn 34, Issue 1, 2011, Pages 1011-1016

  Ohba, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC SENSE; LEGACY PROCESS; LOW ASPECT RATIO; METAL FILLING; PROCESS MARGINS; SELF ALIGNMENT; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH-SILICON-VIA; TOTAL YIELD; WAFER LEVEL; WAFER-SCALE;

ASPECT RATIO; DIES; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; TECHNOLOGY;

THREE DIMENSIONAL;

EID: 79959656904     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3567707     Document Type: Conference Paper

References (16)

1. J.F. Gibbons et al., EDL-1 (6), 117 (1980).
2. S. Kawamura et al., EDL-4 (10), 366 (1983).
3. S-M. Jung et al., IEDM Tech. Dig., 265 (2004).
4. J.A. Burns et al., IEEE Trans. Elect. Dev. 53, 2507 (2006).
5. F. Liu et al., IEDM Tech. Digest, 599 (2008).
6. T. Ohba et al., Microelectronic Eng., Elsevier, 87, 485 (2010).
7. T. Ohba, IEEE ICSICT, 70 (2010).
8. N. Maeda et al., AMC 2008, MRS, 501 (2009).
9. H. Kitada et al., IEEE Proc. of IITC, 107 (2009).
10. K. Fujimoto et al., Solid-State Sensors, Actuators and Microsystems Conference, 1877 (2009).
11. T. Ohba, IEEE Proc. of IITC, 12.1 (2010).
12. T. Ohba et al., IEICE Trans, and Electronics, J93-C (11), 464 (2010).
13. H. Kitada et al., IEEE Proc. of IITC, 9.6 (2010).
14. N. Maeda et al., IEEE VLSI Symp. 150 (2010).
15. Y. S. Kim et al., IEDM Tech. Dig. 365 (2009).
16. T. Ohba, Pioneer, ITRI/EOL, Taiwan, Nov., 51 (2010).