-
1
-
-
18144415503
-
Systematic defects in deep sub-micron technologies
-
11.1, Proceedings - International Test Conference 2004
-
B. Kruseman, et al., "Systematic Defects in Deep Sub-Micron Technologies," International Test Conference pp. 290-299, 2004. (Pubitemid 40610027)
-
(2004)
Proceedings - International Test Conference
, pp. 290-299
-
-
Kruseman, B.1
Majhi, A.2
Hora, C.3
Eichenberger, S.4
Meirlevede, J.5
-
2
-
-
79951636612
-
Diagnosis-enhanced extraction of defect density and size distributions from digital logic ICs
-
J. E. Nelson, W. Maly, and R. D. Blanton, "Diagnosis-Enhanced Extraction of Defect Density and Size Distributions from Digital Logic ICs," SRC TECHCON, 2007.
-
(2007)
SRC TECHCON
-
-
Nelson, J.E.1
Maly, W.2
Blanton, R.D.3
-
3
-
-
34548808679
-
Analyzing volume diagnosis results with statistical learning for yield improvement
-
T. Huaxing, et al., "Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement," European Test Symposium, pp. 145-150, 2007.
-
(2007)
European Test Symposium
, pp. 145-150
-
-
Huaxing, T.1
-
4
-
-
39749125531
-
A rapid yield learning flow based on production integrated layout-aware diagnosis
-
K. Martin, et al., "A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis," International Test Conference, pp. 1-10, 2006.
-
(2006)
International Test Conference
, pp. 1-10
-
-
Martin, K.1
-
5
-
-
70350376736
-
Controlling DPPM through volume diagnosis
-
X. Yu, et al., "Controlling DPPM through Volume Diagnosis," VLSI Test Symposium, pp. 134-139, 2009.
-
(2009)
VLSI Test Symposium
, pp. 134-139
-
-
Yu, X.1
-
6
-
-
67249085977
-
Efficiently performing yield enhancements by identifying dominant physical root cause from test fail data
-
M. Sharma, et al., "Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data," International Test Conference, pp. 1-9, 2008.
-
(2008)
International Test Conference
, pp. 1-9
-
-
Sharma, M.1
-
7
-
-
21244464766
-
Value-added defect testing techniques
-
DOI 10.1109/MDT.2005.74
-
J. Jahangiri and D. Abercrombie, "Value-Added Defect Testing Techniques," IEEE Design & Test of Computers, vol. 22, pp. 224-231, 2005. (Pubitemid 40889822)
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.3
, pp. 224-231
-
-
Jahangiri, J.1
Abercrombie, D.2
-
8
-
-
70350417471
-
Bridging DFM analysis and volume diagnostics for yield learning - A case study
-
R. Turakhia, et al., "Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study," VLSI Test Symposium, pp. 167-172, 2009.
-
(2009)
VLSI Test Symposium
, pp. 167-172
-
-
Turakhia, R.1
-
9
-
-
39749170502
-
A logic diagnosis methodology for improved localization and extraction of accurate defect behavior
-
R. Desineni, O. Poku, and R. D. Blanton, "A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior," International Test Conference, pp. 1-10, 2006.
-
(2006)
International Test Conference
, pp. 1-10
-
-
Desineni, R.1
Poku, O.2
Blanton, R.D.3
-
10
-
-
0025480229
-
Diagnosing CMOS bridging faults with stuck-at fault dictionaries
-
S. D. Millman, E. J. McCluskey, and J. M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries," International Test Conference, pp. 860-870, 1990.
-
(1990)
International Test Conference
, pp. 860-870
-
-
Millman, S.D.1
McCluskey, E.J.2
Acken, J.M.3
-
12
-
-
0035687352
-
Diagnosing combinational logic designs using the Single Location At-a-Time (SLAT) paradigm
-
T. Bartenstein, et al., "Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm," International Test Conference, pp. 287-296, 2001. (Pubitemid 34064800)
-
(2001)
IEEE International Test Conference (TC)
, pp. 287-296
-
-
Bartenstein, T.1
Heaberlin, D.2
Huisman, L.3
Sliwinski, D.4
-
13
-
-
0036446077
-
Multiples, models, and the search for meaning: Improving per-test fault diagnosis
-
D. B. Lavo, I. Hartanto, and T. Larrabee, "Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis," International Test Conference, pp. 250-259, 2002. (Pubitemid 35411426)
-
(2002)
IEEE International Test Conference (TC)
, pp. 250-259
-
-
Lavo, D.B.1
Hartanto, I.2
Larrabee, T.3
-
14
-
-
0030383964
-
Beyond the byzantine generals: Unexpected behavior and bridging fault diagnosis
-
D. B. Lavo, T. Larrabee, and B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis," International Test Conference, pp. 611-619, 1996.
-
(1996)
International Test Conference
, pp. 611-619
-
-
Lavo, D.B.1
Larrabee, T.2
Chess, B.3
-
15
-
-
0036444432
-
A persistent diagnostic technique for unstable defects
-
Y. Sato, et al., "A Persistent Diagnostic Technique for Unstable Defects," International Test Conference, pp. 242-249, 2002. (Pubitemid 35411425)
-
(2002)
IEEE International Test Conference (TC)
, pp. 242-249
-
-
Sato, Y.1
Yamazaki, I.2
Yamanaka, H.3
Ikeda, T.4
Takakura, M.5
-
16
-
-
35148837943
-
Diagnosis of full open defects in interconnecting lines
-
R. Rodriguez-Montanes, et al., "Diagnosis of Full Open Defects in Interconnecting Lines," VLSI Test Symposium, pp. 158-166, 2007.
-
(2007)
VLSI Test Symposium
, pp. 158-166
-
-
Rodriguez-Montanes, R.1
-
17
-
-
70350741519
-
Automated failure population creation for validating integrated circuit diagnosis methods
-
W. C. Tam, O. Poku, and R. D. Blanton, "Automated Failure Population Creation for Validating Integrated Circuit Diagnosis Methods," Design Automation Conference, pp. 708-713, 2009.
-
(2009)
Design Automation Conference
, pp. 708-713
-
-
Tam, W.C.1
Poku, O.2
Blanton, R.D.3
-
18
-
-
66749090170
-
-
2.3 ed. Napa, CA.: Accellera Organization, Inc.
-
"The Verilog-AMS Language Reference Manual," 2.3 ed. Napa, CA.: Accellera Organization, Inc., 2008.
-
(2008)
The Verilog-AMS Language Reference Manual
-
-
-
20
-
-
0002936338
-
Carafe: An inductive fault analysis tool for CMOS VLSI circuits
-
A. Jee and F. J. Ferguson, "Carafe: an Inductive Fault Analysis Tool for CMOS VLSI Circuits," VLSI Test Symposium, pp. 92-98, 1993.
-
(1993)
VLSI Test Symposium
, pp. 92-98
-
-
Jee, A.1
Ferguson, F.J.2
-
21
-
-
0030284911
-
Rapid failure analysis using contamination-defect-fault (CDF) simulation
-
PII S0894650796081213
-
J. Khare and W. Maly, "Rapid Failure Analysis Using Contamination-Defect-Fault (CDF) Simulation," IEEE Transactions on Semiconductor Manufacturing, vol. 9, pp. 518-526, 1996. (Pubitemid 126776283)
-
(1996)
IEEE Transactions on Semiconductor Manufacturing
, vol.9
, Issue.4
, pp. 518-526
-
-
Khare, J.1
Maly, W.2
-
22
-
-
0029547746
-
Inductive contamination analysis (ICA) with SRAM application
-
J. Khare and W. Maly, "Inductive Contamination Analysis (ICA) with SRAM Application," International Test Conference, pp. 552-560, 1995.
-
(1995)
International Test Conference
, pp. 552-560
-
-
Khare, J.1
Maly, W.2
-
23
-
-
0029698230
-
Fault characterization of standard cell libraries using inductive contamination analysis (ICA)
-
J. Khare, W. Maly, and N. Tiday, "Fault Characterization of Standard Cell Libraries Using Inductive Contamination Analysis (ICA)," VLSI Test Symposium, pp. 405-413, 1996.
-
(1996)
VLSI Test Symposium
, pp. 405-413
-
-
Khare, J.1
Maly, W.2
Tiday, N.3
-
24
-
-
10444222909
-
Benchmarking diagnosis algorithms with a diverse set of IC deformations
-
17.3, Proceedings - International Test Conference 2004
-
T. Vogels, et al., "Benchmarking Diagnosis Algorithms with a Diverse Set of IC Deformations," International Test Conference, pp. 508-517, 2004. (Pubitemid 40610050)
-
(2004)
Proceedings - International Test Conference
, pp. 508-517
-
-
Vogels, T.1
Zanon, T.2
Desineni, R.3
Blanton, R.D.4
Maly, W.5
Brown, J.G.6
Nelson, J.E.7
Fei, Y.8
Huang, X.9
Gopalakrishnan, P.10
Mishra, M.11
Rovner, V.12
Tiwary, S.13
-
26
-
-
0027271157
-
Fast hierarchical multi-level fault simulation of sequential circuits with switch level accuracy
-
W. Meyer and R. Camposano, "Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy," Design Automation Conference, pp. 515-519, 1993. (Pubitemid 23673211)
-
(1993)
Proceedings - Design Automation Conference
, pp. 515-519
-
-
Meyer Wolfgang1
Camposano Raul2
-
27
-
-
84893629710
-
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
-
M. B. Santos and J. P. Teixeira, "Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL," Design, Automation and Test in Europe, pp. 549-553, 1999.
-
(1999)
Design, Automation and Test in Europe
, pp. 549-553
-
-
Santos, M.B.1
Teixeira, J.P.2
-
28
-
-
33750577694
-
Defect modeling using fault tuples
-
DOI 10.1109/TCAD.2006.870836, 1715429
-
R. D. Blanton, K. N. Dwarakanath, and R. Desineni, "Defect Modeling Using Fault Tuples," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 2450-2464, 2006. (Pubitemid 44679365)
-
(2006)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.25
, Issue.11
, pp. 2450-2464
-
-
Blanton, R.D.1
Dwarakanath, K.N.2
Desineni, R.3
-
29
-
-
49749097137
-
Physically-aware N-detect test pattern selection
-
Y.-T. Lin, et al., "Physically-Aware N-Detect Test Pattern Selection," Design, Automation and Test in Europe, pp. 634-639, 2008.
-
(2008)
Design, Automation and Test in Europe
, pp. 634-639
-
-
Lin, Y.-T.1
-
30
-
-
79951616785
-
Automatic classification of bridge defects
-
J. E. Nelson, W. C. Tam, and R. D. Blanton, "Automatic Classification of Bridge Defects," International Test Conference, p. 10.3, 2010.
-
(2010)
International Test Conference
, pp. 103
-
-
Nelson, J.E.1
Tam, W.C.2
Blanton, R.D.3
-
32
-
-
0002609165
-
A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
-
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," International Symposium on Circuits and Systems, pp. 1929-1934, 1985.
-
(1985)
International Symposium on Circuits and Systems
, pp. 1929-1934
-
-
Brglez, F.1
Fujiwara, H.2
-
34
-
-
0036443193
-
Fault tuples in diagnosis of deep-submicron circuits
-
R. D. Blanton, et al., "Fault Tuples in Diagnosis of Deep-Submicron Circuits," International Test Conference, pp. 233-241, 2002. (Pubitemid 35411424)
-
(2002)
IEEE International Test Conference (TC)
, pp. 233-241
-
-
Blanton, R.D.S.1
Chen, J.T.2
Desineni, R.3
Dwarakanath, K.N.4
Maly, W.5
Vogels, T.J.6
-
36
-
-
70350710864
-
-
ed. San Jose, CA: Cadence Design Systems Inc
-
"The Diva Reference Manual," ed. San Jose, CA: Cadence Design Systems Inc.
-
The Diva Reference Manual
-
-
-
38
-
-
77953907786
-
-
ed. Mountain View, CA.: Synopsys Inc.
-
"The Tetramax User Guide," ed. Mountain View, CA.: Synopsys Inc., 2009.
-
(2009)
The Tetramax User Guide
-
-
|