Hardware-software co-design of an iris recognition algorithm

IET Information Security

Volumn 5, Issue 1, 2011, Pages 60-68

  Lopez M ^a   Daugman, J ^b   Canto E ^c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^c UNIVERSITAT ROVIRA I VIRGILI   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SPEED; CO-PROCESSORS; EXECUTION TIME; HARDWARE SOFTWARE CODESIGN; IRIS RECOGNITION ALGORITHM; SOFTWARE SOLUTION; SOFTWARE-BASED; SPARTAN-3; SYSTEM ARCHITECTURES;

ALGORITHMS; BIOMETRICS; MICROPROCESSOR CHIPS;

EMBEDDED SOFTWARE;

EID: 79957607976     PISSN: 17518709     EISSN: 17518717     Source Type: Journal    
DOI: 10.1049/iet-ifs.2009.0267     Document Type: Article

References (23)

1. Fingerprint Verification Competition 2006 (FVC2006), available at http://bias.csr.unibo.it/fvc
2. Daugman, J.G.:'Probing the uniqueness and randomness of IrisCodes: results from 200 billion iris pair comparisons', Proc. IEEE, 2006, 94, (11), p. 1927-1935 10.1109/JPROC.2006.884092 0018-9219 (Pubitemid 46445563)
3. Ratha, N., Rover, D., and Jain, A.K.:'An FPGA-based point pattern matching processor with application to fingerprint matching', CAMP'95, Italy, 1995, p. 394-401
4. Ratha, N., Rover, D., and Jain, A.K.:'Fingerprint matching on Splash 2', Buell, D., Arnold, J., Kleinfolder, W., FPGAs in a custom computing machine, (IEEE Computer Society Press, 1996), p. 117-140
5. Cantó, E., Canyellas, N., Fons, M., Fons, F., and López, M.:'FPGA implementation of the ridge line following fingerprint algorithm', Proc. 14th Int. Conf. on Field-Programmable Logic and Applications (FPL'2004), Antwerp, Belgium, August/September, 2004, p. 1087-1089 (Pubitemid 39210607)
6. Fons, M., Fons, F., Cantó, E., and López, M.:'Hardware-software co-design of a fingerprint matcher on card', Proc. 2006 IEEE Int. Conf. on Electro Information Technology (EIT'2006), Michigan, USA, May, 2006
7. Lopez, M., Cantó, E., and Fons, M.:'Hardware-software co-design of a fingerprint image enhancement algorithm', 32nd, Annual Conf. IEEE Industrial Electronics, Paris, France, November, 2006
8. Yang, S., Sakiyama, K., and Verbauwhebe, I.:'A compact and efficient fingerprint verification system for secure embedded devices', IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP 2005), March, 2005, p. 609-612
9. Yang, S., Sakiyama, K., and Verbauwhebe, I.:'Efficient and secure fingerprint verification for embedded devices', EURASIP J. Appl. Signal Process., 2006, 2006, (3), p. 1-11 10.1155/ASP/2006/58263 1110-8657
10. Schaumont, P., Hwang, D., and Verbauwhede, I.:'Platform-based design for an embedded fingerprint authentication device', IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005, 24, (12), p. 1929-1936 10.1109/TCAD.2005.853709 0278-0070 (Pubitemid 41807358)
11. Lai, H.-C., Savvides, M., and Chen, T.:'Proposed FPGA hardware architecture for high frame rate (≫100fps) face detection using feature cascade classifiers', First IEEE Int. Conf. on Biometrics: Theory, Applications, and Systems, 2007, BTAS 2007, Washington, September, 2007, p. 1-6, EE.UU
12. Ramos, R., López, M., Cantó, E., and Rodriguez, L.:'SVM speaker verification system-based on low-cost FPGA', Proc. 19th Int. Conf. on Field-Programmable Logic and Applications (FPL'2009), Prague, Czech Republic, August/September, 2009, p. 582-586
13. Daugman, J.G.:'How iris recognition works', IEEE Trans. Circuits Syst. Video Technol., 2004, 14, (1), p. 21-30 10.1109/TCSVT.2003.818350 1051-8215
14. Daugman, J.G.:'New methods in Iris recognition', IEEE Trans. Syst. Man Cybern. B, Cybern., 2007, 37, (5), p. 1167-1175 10.1109/TSMCB.2007.903540 1083-4419 (Pubitemid 47534585)
15. Daugman, J.G.:'The importance of being random: statistical principles of iris recognition', Pattern Recognit., 2003, 36, p. 279-291 10.1016/S0031- 3203(02)00030-4 0031-3203
16. Gupta, R.K., and De Michelli, G.:'Hardware-software co-synthesis for digital systems', IEEE Des. Test Comput., 1993, 10, p. 29-41 10.1109/54.232470 0740-7475
17. Henkel, J., and Ernst, R.:'An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques', IEEE Trans. Very Large Scale Integr. Syst., 2001, 9, (2), p. 273-289 10.1109/92.924041 1063-8210 (Pubitemid 32583515)
18. Steve, F.:'ARM system-on-chip architecture', 2nd (Addison Wesley, 2000)
19. TM 2.4 Specifications, available at http://www.l1id.com/ pages/148-specifications
20. MicroBlaze Processor Reference Guide, available at http://www.xilinx.com/ support/
21. Floating Point Operator v3.0, Xilinx LogicCore, available at http://www.xilinx.com/products/ipcenter/floating-pt.htm
22. ® Spartan™-3 Development Kit User Guide, available at https://www.em.avnet.com
23. Ali, M.A.:'Leonardo spectrum getting started features document', available at http://www.mentor.com/products/fpga-pld/synthesis/leonardo- spectrum/index.cfm