Priority division: A high-speed shared-memory bus arbitration with bounded latency

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 1497-1500

  Shah, Hardik ^a   Raabe, Andreas ^a   Knoll, Alois ^b  

^a FORTISS GMBH   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE-CASE; BANDWIDTH DISTRIBUTION; BOUNDED LATENCY; BUS ARBITRATION; HIGH-SPEED; INTERCHIP COMMUNICATIONS; MEDIUM SIZE; MULTI-PROCESSORS; ON CHIP COMMUNICATION; PROCESSING ELEMENTS; REAL TIME; REAL-TIME APPLICATION; RESPONSE TIME; ROUND ROBIN; SHARED BUS; SHARED MEMORIES; STATIC PRIORITY; SYSTEMS ON CHIPS; TIME FRAME; WORST-CASE PERFORMANCE;

BANDWIDTH; MICROPROCESSOR CHIPS; TIME DIVISION MULTIPLE ACCESS;

MULTIPROCESSING SYSTEMS;

EID: 79957571977     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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