A high-level analytical model for application specific CMP design exploration

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 1095-1100

  Cassidy, Andrew ^a   Yu, Kai ^b   Zhou, Haolang ^a   Andreou, Andreas G ^a  

^a Johns Hopkins University   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; APPLICATION SPECIFIC; ARCHITECTURAL ELEMENT; AUTOMATED APPROACH; CHIP MULTIPROCESSOR; DESIGN EXPLORATION; ENERGY-DELAY; MICRO ARCHITECTURES; MODEL PARAMETERS; OPTIMIZATION PROCESS; PERFORMANCE GAIN;

AUTOMATION; CACHE MEMORY; COMPUTER SIMULATION; CONSTRAINED OPTIMIZATION; GLOBAL OPTIMIZATION; MATHEMATICAL MODELS; MODELS; SPEECH RECOGNITION;

DESIGN;

EID: 79957569993     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. M. Hill and M. Marty, "Amdahl's law in the multicore era," Computer, vol. 41, no. 7, pp. 33-38, 2008.
2. D. H. Woo and H. Lee, "Extending Amdahl's law for energy-efficient computing in the many-core era," Computer, vol. 41, no. 12, pp. 24-31, Dec 2008.
3. T. Oh, H. Lee, K. Lee, and S. Cho, "An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor," in IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society, 2009, pp. 181-186.
4. D. Chandra, F. Guo, S. Kim, and Y. Solihin, "Predicting inter-thread cache contention on a chip multi-processor architecture," in International Symposium on High-Performance Computer Architecture (HPCA). Washington, DC, USA: IEEE Computer Society, 2005, pp. 340-351.
5. X. Chen and T. Aamodt, "A first-order fine-grained multithreaded throughput model," in International Symposium on High Performance Computer Architecture, (HPCA), 2009, pp. 329-340.
6. Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron, "CMP design space exploration subject to physical constraints," International Symposium on High-Performance Computer Architecture, pp. 15-26, Feb 2006.
7. M. Monchiero, R. Canal, and A. González, "Design space exploration for multicore architectures: a power/performance/thermal view," International Conference on Supercomputing (ICS), Jun 2006.
8. A. Cassidy and A. G. Andreou, "Analytical methods for the design and optimization of chip-multiprocessor architectures," 43rd Annual Conference on Information Sciences and Systems (CISS 2009), pp. 482-487, Mar 2009.
9. S. Borkar, "Thousand core chips: a technology perspective," Proceedings of the 44th annual Design Automation Conference (DAC '07), Jun 2007.
10. S. Przybylski, M. Horowitz, and J. Hennessy, "Characteristics of performance-optimal multi-level cache hierarchies," International Symposium on Computer Architecture (ISCA), pp. 114-121, Apr 1989.
11. A. Hartstein, V. Srinivasan, T. Puzak, and P. Emma, "On the Nature of Cache Miss Behavior: Is It √2 ?" The Journal of Instruction-Level Parallelism, vol. 10, 2008.
12. R. Matick, T. Heller, and M. Ignatowski, "Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory," Ibm J Res Dev, vol. 45, no. 6, pp. 819-842, Jun 2001.
13. D. Gross and C. M. Harris, Fundamentals of queueing theory, 3rd ed. John Wiley & Sons, Inc., 1998.
14. T. Austin, E. Larson, and D. Ernst, "Simplescalar: an infrastructure for computer system modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb 2002.
15. P. Placeway, S. Chen, M. Eskenazi, U. Jain, V. Parikh, B. Raj, M. Ravishankar, R. Rosenfeld, K. Seymore, M. Siegler et al., "The 1996 Hub-4 Sphinx-3 System," in Proc. DARPA Speech recognition workshop, 1997, pp. 85-89.
16. K. Yu and R. A. Rutenbar, "Profiling large-vocabulary continuous speech recognition on embedded devices: A hardware resource sensitivity analysis," Interspeech, pp. 1923-1926, Sep 2009.
17. "AMD website," http://www.amd.com/, 2009.
18. L. Gwennap, "PPC 604 Powers Past Pentium," Microprocessor Report, pp. 5-8, 1994.
19. "DDR2 SDRAM Device Operating & Timing Diagram," Samsung Datasheet, 2007.
20. M. Kistler, M. Perrone, and F. Petrini, "Cell multiprocessor communication network: built for speed," IEEE MICRO, vol. 26, no. 3, pp. 10-23, May 2006.
21. S. Young, P. Woodland, and W. Byrne, "HTK-Hidden Markov Model Toolkit," Cambridge University Engineering Department, 1999.
22. R. Burden and J. Faires, Numerical Analysis, 5th ed. PWS Publishing Company, 1993.